diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedIceLake.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedIceLake.td | 42 |
1 files changed, 19 insertions, 23 deletions
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td index c49ebf4bf735..35723399100a 100644 --- a/llvm/lib/Target/X86/X86SchedIceLake.td +++ b/llvm/lib/Target/X86/X86SchedIceLake.td @@ -388,14 +388,14 @@ defm : ICXWriteResPair<WriteVecIMulZ, [ICXPort05], 5, [1], 1, 7>; defm : ICXWriteResPair<WritePMULLD, [ICXPort01], 10, [2], 2, 6>; // Vector PMULLD. defm : ICXWriteResPair<WritePMULLDY, [ICXPort01], 10, [2], 2, 7>; defm : ICXWriteResPair<WritePMULLDZ, [ICXPort05], 10, [2], 2, 7>; -defm : ICXWriteResPair<WriteShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector shuffles. -defm : ICXWriteResPair<WriteShuffleX, [ICXPort5], 1, [1], 1, 6>; -defm : ICXWriteResPair<WriteShuffleY, [ICXPort5], 1, [1], 1, 7>; -defm : ICXWriteResPair<WriteShuffleZ, [ICXPort5], 1, [1], 1, 7>; -defm : ICXWriteResPair<WriteVarShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector variable shuffles. -defm : ICXWriteResPair<WriteVarShuffleX, [ICXPort5], 1, [1], 1, 6>; -defm : ICXWriteResPair<WriteVarShuffleY, [ICXPort5], 1, [1], 1, 7>; -defm : ICXWriteResPair<WriteVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; +defm : ICXWriteResPair<WriteShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector shuffles. +defm : ICXWriteResPair<WriteShuffleX, [ICXPort15], 1, [1], 1, 6>; +defm : ICXWriteResPair<WriteShuffleY, [ICXPort15], 1, [1], 1, 7>; +defm : ICXWriteResPair<WriteShuffleZ, [ICXPort5], 1, [1], 1, 7>; +defm : ICXWriteResPair<WriteVarShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector variable shuffles. +defm : ICXWriteResPair<WriteVarShuffleX, [ICXPort15], 1, [1], 1, 6>; +defm : ICXWriteResPair<WriteVarShuffleY, [ICXPort15], 1, [1], 1, 7>; +defm : ICXWriteResPair<WriteVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; defm : ICXWriteResPair<WriteBlend, [ICXPort5], 1, [1], 1, 6>; // Vector blends. defm : ICXWriteResPair<WriteBlendY,[ICXPort5], 1, [1], 1, 7>; defm : ICXWriteResPair<WriteBlendZ,[ICXPort5], 1, [1], 1, 7>; @@ -663,7 +663,10 @@ def ICXWriteResGroup3 : SchedWriteRes<[ICXPort5]> { } def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r", "KMOV(B|D|Q|W)kr", - "UCOM_F(P?)r")>; + "UCOM_F(P?)r", + "VPBROADCAST(D|Q)rr", + "(V?)PALIGNR(Y|Z|Z128|Z256)?rri", + "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z128|Z256)?rr")>; def ICXWriteResGroup4 : SchedWriteRes<[ICXPort6]> { let Latency = 1; @@ -1296,19 +1299,10 @@ def ICXWriteResGroup92 : SchedWriteRes<[ICXPort5,ICXPort23]> { let ResourceCycles = [1,1]; } def: InstRW<[ICXWriteResGroup92], (instregex "VMOVSDZrm(b?)", - "VMOVSSZrm(b?)")>; - -def ICXWriteResGroup92a : SchedWriteRes<[ICXPort5,ICXPort23]> { - let Latency = 6; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[ICXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm", - "(V?)PMOV(SX|ZX)BQrm", - "(V?)PMOV(SX|ZX)BWrm", - "(V?)PMOV(SX|ZX)DQrm", - "(V?)PMOV(SX|ZX)WDrm", - "(V?)PMOV(SX|ZX)WQrm")>; + "VMOVSSZrm(b?)", + "VPBROADCAST(B|W)(Z128)?rm", + "(V?)PALIGNR(Z128)?rmi", + "(V?)PACK(U|S)S(DW|WB)(Z128)?rm")>; def ICXWriteResGroup93 : SchedWriteRes<[ICXPort5,ICXPort015]> { let Latency = 7; @@ -1546,7 +1540,9 @@ def ICXWriteResGroup119 : SchedWriteRes<[ICXPort5,ICXPort23]> { } def: InstRW<[ICXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", "VPBROADCASTB(Z|Z256)rm(b?)", - "VPBROADCASTW(Z|Z256)rm(b?)")>; + "VPBROADCASTW(Z|Z256)rm(b?)", + "(V?)PALIGNR(Y|Z|Z256)rmi", + "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z256)rm")>; def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm, VPBROADCASTWYrm, VPMOVSXBDYrm, |