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* [AArch64] Ampere1 does not support MTEPhilipp Tomsich2022-05-112-3/+2
* [AArch64] Support for Ampere1 corePhilipp Tomsich2022-05-1115-4/+1209
* [AArch64] Add native CPU detection for Ampere1Philipp Tomsich2022-05-112-0/+10
* [IPSCCP] Support unfeasible default dests for switch.Florian Hahn2022-05-112-7/+166
* [InstCombine] Fix scalable-vector bitwise select matchingFraser Cormack2022-05-112-1/+36
* [InstCombine] add scalable vector test for logical select; NFCSanjay Patel2022-05-111-0/+19
* [HIP] Fix HIP include pathYaxun (Sam) Liu2022-05-113-9/+9
* Fix test for c7ee0b8bda8b32a800bc01e9151b364446a6e1b1Brad Smith2022-05-111-3/+0
* [Clang] Fix the guaranteed alignment of memory returned by malloc/new on OpenBSDMark Kettenis2022-05-114-3/+12
* [Driver][Linux] Remove D.Dir+"/../lib" from default search paths for LLVM_ENA...Fangrui Song2022-05-112-13/+5
* [MC][ELF] Improve st_size propagation ruleFangrui Song2022-05-112-5/+24
* [MC][test] Improve offset.sFangrui Song2022-05-111-111/+46
* Bump version to 14.0.4Tom Stellard2022-05-118-9/+9
* [libc++abi] Remove XFAIL on arm64Louis Dionne2022-05-101-3/+0
* Bump version to 14.0.3llvmorg-14.0.3Tom Stellard2022-04-288-9/+9
* workflows: Add a test to ensure that the LLVM version is correctTom Stellard2022-04-282-0/+58
* [RISCV] Fix crash for section alignment with .option norvcllvmorg-14.0.2Luís Marques2022-04-253-3/+21
* [asan] Always skip first object from dl_iterate_phdrMichael Forney2022-04-251-18/+12
* [RISCV] Don't emit fractional VIDs with negative stepsFraser Cormack2022-04-252-8/+9
* [RISCV] Add another test showing incorrect BUILD_VECTOR loweringFraser Cormack2022-04-251-0/+15
* [RISCV] Fix lowering of BUILD_VECTORs as VID sequencesFraser Cormack2022-04-252-35/+44
* [RISCV] Add tests showing incorrect BUILD_VECTOR loweringFraser Cormack2022-04-251-0/+21
* [llvm-mt] Add support /notify_updateAlex Brachet2022-04-253-2/+41
* [RISCV] Only try LUI+SH*ADD+ADDI for int materialization if LUI+ADDI+SH*ADD f...Craig Topper2022-04-252-26/+64
* [ELF] --emit-relocs: fix missing STT_SECTION when the first input section is ...Fangrui Song2022-04-252-17/+78
* [libcxx] Add some missing xlocale wrapper functions for OpenBSDBrad Smith2022-04-251-0/+20
* [LV] Remove stray debug dump added in 0d2efbb8b82c.Florian Hahn2022-04-251-1/+0
* [LV] Always use add to add scalar iv and (startidx + step) for ints.Florian Hahn2022-04-252-10/+10
* [LV] Add test case for PR54427.Florian Hahn2022-04-251-0/+46
* [InstCombine] canonicalize select with signbit testSanjay Patel2022-04-214-44/+61
* [x86] Fix infinite loop inside DAG combiner with lzcnt feature.Pierre Gousseau2022-04-212-13/+42
* [Clang][Fortify] drop inline decls when redeclaredserge-sans-paille2022-04-182-2/+38
* Reland "[llvm][AArch64] Insert "bti j" after call to setjmp"David Spickett2022-04-1815-6/+284
* [DebugInfo][InstrRef] Avoid a crash from mixed variable location modesJeremy Morse2022-04-1811-11/+158
* Force GHashCell to be 8-byte-aligned.Eli Friedman2022-04-181-1/+5
* [compiler-rt] Implement __clear_cache on FreeBSD/powerpcCarlo Marcelo Arenas Belón2022-04-181-1/+4
* [PowerPC] Allow absolute expressions in relocationsNemanja Ivanovic2022-04-188-45/+69
* [CMake] Update cache file for Win to ARM Linux cross toolchain builders. NFC.Vladimir Vereschaka2022-04-141-2/+3
* [CMake] Replace `TARGET_TRIPLE` with `TOOLCHAIN_TARGET_TRIPLE` for Win-to-Arm...Vladimir Vereschaka2022-04-141-65/+65
* [CMake] Update cache file for Win to ARM cross tooolchain. NFC.Vladimir Vereschaka2022-04-141-5/+0
* [CMake] Use CMAKE_SYSROOT to build libs for Win to ARM cross tooolchain. NFC.Vladimir Vereschaka2022-04-141-67/+84
* [LLD][COFF] Fix TypeServerSource matcher with more than one collisionTobias Hieta2022-04-143-13/+15
* [lld][COFF] Fix TypeServerSource lookup on GUID collisionsTobias Hieta2022-04-147-2/+2426
* [AArch64][LOH] Don't ignore regmasks in bundles by iterating over instrs.Ahmed Bougacha2022-04-142-1/+10
* [InstCombine] try to fold low-mask of ashr to lshrSanjay Patel2022-04-142-4/+16
* [InstCombine] add tests for low-mask of ashr; NFCSanjay Patel2022-04-141-8/+72
* [LV] Handle zero cost loops in selectInterleaveCount.Florian Hahn2022-04-142-10/+62
* [RISCV][NFC] Add missing lit.local.cfg in test/CodeGen/MIR/RISCV/Kito Cheng2022-04-141-0/+2
* [RISCV] Fixing stack offset for RVV object with vararg in stack.Kito Cheng2022-04-142-6/+21
* [RISCV] Pre-commit for fixing stack offset for RVV objectKito Cheng2022-04-141-0/+220
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