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path: root/lib/Target/R600/R600Instructions.td
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* R600: Use new fmad node.Matt Arsenault2015-02-201-1/+1
* R600/SI: Don't set isCodeGenOnly = 1 on all instructionsTom Stellard2015-02-181-0/+5
* R600: Fix operand encoding errorMatt Arsenault2015-02-181-0/+1
* R600/SI: Implement correct f64 fdivMatt Arsenault2015-02-141-1/+1
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-3/+4
* R600/SI: Custom lower froundMatt Arsenault2015-01-211-12/+0
* R600/SI: Use unordered not equal instructionsMatt Arsenault2014-12-111-2/+3
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-261-1/+1
* R600/SI: Start implementing an assemblerTom Stellard2014-11-141-0/+1
* R600/SI: Fix fmin_legacy / fmax_legacy matching for SIMatt Arsenault2014-11-131-2/+3
* R600: Don't unnecessarily repeat the register classMatt Arsenault2014-11-021-5/+5
* R600: FMA is VecALU only instructionJan Vesely2014-10-141-1/+1
* R600: Fix FROUNDJan Vesely2014-09-051-3/+6
* R600: Add FMA instructions for EvergreenMatt Arsenault2014-07-241-0/+5
* R600: Match rcp node on pre-SIMatt Arsenault2014-07-241-1/+6
* R600/SI: fix shadow mapping for 1D and 2D array texturesMarek Olsak2014-07-111-1/+1
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-241-3/+6
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-201-4/+1
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-191-1/+1
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-0/+54
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-25/+59
* R600: Set correct InstrItinClass for instructions using *Helper classesTom Stellard2014-06-111-3/+3
* R600: Expand mul24 for GPUs without itMatt Arsenault2014-05-221-2/+2
* R600: Expand mad24 for GPUs without itMatt Arsenault2014-05-221-0/+6
* R600: Reorganize tablegen instruction definitionsTom Stellard2014-03-241-781/+2
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-171-6/+11
* R600: LDS instructions shouldn't implicitly define OQAPTom Stellard2014-03-131-2/+0
* R600: Remove unnecessary build_vector pattern.Matt Arsenault2014-02-261-3/+0
* Fix known typosAlp Toker2014-01-241-1/+1
* R600: Disable the BFE patternTom Stellard2014-01-231-1/+3
* R600: Add some missing CF instruction definitions to the .td files.Tom Stellard2014-01-221-0/+7
* R600: CF_PUSH is the same on Evergreen and CaymanTom Stellard2014-01-221-3/+4
* R600: MOVA is vector onlyTom Stellard2014-01-221-1/+1
* R600: Allow ftruncTom Stellard2013-12-201-0/+3
* R600: Workaround for cayman loop bugVincent Lejeune2013-12-021-0/+4
* R600: Add support for ISD::FROUNDTom Stellard2013-11-271-4/+14
* R600/SI: Fixing handling of condition codesTom Stellard2013-11-221-3/+3
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-1/+0
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-111-1/+1
* R600: Clear the VPM bit of export instructions.Vincent Lejeune2013-10-131-4/+4
* R600: Add a ldptr intrinsic to support MSAA.Vincent Lejeune2013-10-021-0/+4
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-011-0/+1
* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-011-1/+1
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-281-43/+11
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-281-48/+0
* R600: Add support for LDS atomic subtractAaron Watry2013-09-061-0/+4
* R600: Add support for local memory atomic addTom Stellard2013-09-051-7/+35
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-041-20/+6
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-0/+12
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-3/+21
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