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* R600: Use new fmad node.Matt Arsenault2015-02-201-1/+1
| | | | | | | | | | | This enables a few useful combines that used to only use fma. Also since v_mad_f32 apparently does not support denormals, disable the existing cases that are custom handled if they are requested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230071 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Don't set isCodeGenOnly = 1 on all instructionsTom Stellard2015-02-181-0/+5
| | | | | | | We only need to set this on pseudo instructions which won't be used by the assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229689 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix operand encoding errorMatt Arsenault2015-02-181-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229609 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Implement correct f64 fdivMatt Arsenault2015-02-141-1/+1
| | | | | | This version passes the OpenCL conformance test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229239 91177308-0d34-0410-b5e6-96231b3b80d8
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-3/+4
| | | | | | without a Function argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227638 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Custom lower froundMatt Arsenault2015-01-211-12/+0
| | | | | | | | | This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226682 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use unordered not equal instructionsMatt Arsenault2014-12-111-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224065 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.Craig Topper2014-11-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222801 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Start implementing an assemblerTom Stellard2014-11-141-0/+1
| | | | | | | This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221994 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix fmin_legacy / fmax_legacy matching for SIMatt Arsenault2014-11-131-2/+3
| | | | | | select_cc is expanded on SI, so this was never matched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221941 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Don't unnecessarily repeat the register classMatt Arsenault2014-11-021-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221119 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: FMA is VecALU only instructionJan Vesely2014-10-141-1/+1
| | | | | | | Reviewed-by: Tom Stellard <tom@stellard.net> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219704 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix FROUNDJan Vesely2014-09-051-3/+6
| | | | | | | | | round halfway cases away from zero Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217250 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add FMA instructions for EvergreenMatt Arsenault2014-07-241-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213882 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Match rcp node on pre-SIMatt Arsenault2014-07-241-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213844 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: fix shadow mapping for 1D and 2D array texturesMarek Olsak2014-07-111-1/+1
| | | | | | | | It was conflicting with def TEX_SHADOW_ARRAY, which also handles them. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212829 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-241-3/+6
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211637 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-201-4/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211377 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-191-1/+1
| | | | | | | | These will be used for custom lowering and for library implementations of various math functions, so it's useful to expose these as builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211247 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-0/+54
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211110 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-25/+59
| | | | | | Most of these are no longer used any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210915 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Set correct InstrItinClass for instructions using *Helper classesTom Stellard2014-06-111-3/+3
| | | | | | | | | We weren't doing this before, so all instruction using the *Helper classes were considered for any ALU slot. This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210703 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand mul24 for GPUs without itMatt Arsenault2014-05-221-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand mad24 for GPUs without itMatt Arsenault2014-05-221-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Reorganize tablegen instruction definitionsTom Stellard2014-03-241-781/+2
| | | | | | Each GPU family now has its own file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204615 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-171-6/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204072 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: LDS instructions shouldn't implicitly define OQAPTom Stellard2014-03-131-2/+0
| | | | | | | | | LDS instructions are pseudo instructions which model the OQAP defs and uses within a single instruction. This fixes a hang in the opencv MedianFilter tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203818 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove unnecessary build_vector pattern.Matt Arsenault2014-02-261-3/+0
| | | | | | It is already fully handled in AMDGPUISelDAGToDAG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202312 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Disable the BFE patternTom Stellard2014-01-231-1/+3
| | | | | | | | | | This pattern uses an SDNodeXForm, which isn't being emitted for some reason. I can get it to work by attaching the PatLeaf that has the XForm to the argument in the output pattern, but this results in an immediate being used in a register operand, which the backend can't handle yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199918 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add some missing CF instruction definitions to the .td files.Tom Stellard2014-01-221-0/+7
| | | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199841 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: CF_PUSH is the same on Evergreen and CaymanTom Stellard2014-01-221-3/+4
| | | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199839 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: MOVA is vector onlyTom Stellard2014-01-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199827 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Allow ftruncTom Stellard2013-12-201-0/+3
| | | | | | | | | | | | v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc v3: move ftrunc pattern next to TRUNC definition, it's available since R600 Patch By: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197783 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Workaround for cayman loop bugVincent Lejeune2013-12-021-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196121 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for ISD::FROUNDTom Stellard2013-11-271-4/+14
| | | | | | NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195878 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fixing handling of condition codesTom Stellard2013-11-221-3/+3
| | | | | | | | | We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195514 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-1/+0
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Clear the VPM bit of export instructions.Vincent Lejeune2013-10-131-4/+4
| | | | | | | It makes apparently no change it to set this bit or not but the docs recommand to left it cleared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192552 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a ldptr intrinsic to support MSAA.Vincent Lejeune2013-10-021-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191838 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-011-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191790 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-281-43/+11
| | | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-281-48/+0
| | | | | | | | | | | | This is useful for targets like R600, which only support GT, GE, NE, and EQ condition codes as it removes the need to handle unsupported condition codes in target specific code. There are no tests with this commit, but R600 has been updated to take advantage of this new feature, so its existing selectcc tests are now testing the swapped operands path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191601 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for LDS atomic subtractAaron Watry2013-09-061-0/+4
| | | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190200 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for local memory atomic addTom Stellard2013-09-051-7/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190080 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-041-20/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189979 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189225 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-3/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
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