From df64272c7bdba91493a21fc13c7fdedb3686cc77 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Wed, 17 May 2023 14:19:37 +0800 Subject: [RISCV] Refactor predicates for rvv SDNode patterns. This patch is similar to https://reviews.llvm.org/D150550, it adds accurate predicates for SDNode patterns depending on vector type. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D150754 --- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 854 +++++++++++---------- 1 file changed, 468 insertions(+), 386 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index 970c021297a2..374cffc01dfe 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -144,28 +144,33 @@ class VPatBinarySDNode_XI_E; -multiclass VPatBinarySDNode_VV_VX { - foreach vti = AllIntegerVectors in { - def : VPatBinarySDNode_VV; - def : VPatBinarySDNode_XI; +multiclass VPatBinarySDNode_VV_VX vtilist = AllIntegerVectors> { + foreach vti = vtilist in { + let Predicates = GetVTypePredicates.Predicates in { + def : VPatBinarySDNode_VV; + def : VPatBinarySDNode_XI; + } } } multiclass VPatBinarySDNode_VV_VX_E { foreach vti = AllIntegerVectors in { - def : VPatBinarySDNode_VV_E; - def : VPatBinarySDNode_XI_E; + let Predicates = GetVTypePredicates.Predicates in { + def : VPatBinarySDNode_VV_E; + def : VPatBinarySDNode_XI_E; + } } } @@ -173,6 +178,7 @@ multiclass VPatBinarySDNode_VV_VX_VI : VPatBinarySDNode_VV_VX { foreach vti = AllIntegerVectors in { + let Predicates = GetVTypePredicates.Predicates in def : VPatBinarySDNode_XI { foreach vti = AllFloatVectors in { - def : VPatBinarySDNode_VV; - def : VPatBinarySDNode_VF; + let Predicates = GetVTypePredicates.Predicates in { + def : VPatBinarySDNode_VV; + def : VPatBinarySDNode_VF; + } } } multiclass VPatBinaryFPSDNode_VV_VF_E { foreach vti = AllFloatVectors in { - def : VPatBinarySDNode_VV_E; - def : VPatBinarySDNode_VF_E; + let Predicates = GetVTypePredicates.Predicates in { + def : VPatBinarySDNode_VV_E; + def : VPatBinarySDNode_VF_E; + } } } multiclass VPatBinaryFPSDNode_R_VF { foreach fvti = AllFloatVectors in + let Predicates = GetVTypePredicates.Predicates in def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)), (fvti.Vector fvti.RegClass:$rs1))), (!cast(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) @@ -254,6 +265,7 @@ multiclass VPatBinaryFPSDNode_R_VF { foreach fvti = AllFloatVectors in + let Predicates = GetVTypePredicates.Predicates in def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)), (fvti.Vector fvti.RegClass:$rs1))), (!cast(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW) @@ -266,6 +278,7 @@ multiclass VPatIntegerSetCCSDNode_VV { foreach vti = AllIntegerVectors in { defvar instruction = !cast(instruction_name#"_VV_"#vti.LMul.MX); + let Predicates = GetVTypePredicates.Predicates in def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs2), cc)), (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, @@ -278,6 +291,7 @@ multiclass VPatIntegerSetCCSDNode_VV_Swappable { foreach vti = AllIntegerVectors in { defvar instruction = !cast(instruction_name#"_VV_"#vti.LMul.MX); + let Predicates = GetVTypePredicates.Predicates in def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs2), (vti.Vector vti.RegClass:$rs1), invcc)), (instruction vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, @@ -293,6 +307,7 @@ multiclass VPatIntegerSetCCSDNode_XI< DAGOperand xop_kind> { foreach vti = AllIntegerVectors in { defvar instruction = !cast(instruction_name#_#kind#_#vti.LMul.MX); + let Predicates = GetVTypePredicates.Predicates in def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1), (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)), (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>; @@ -308,12 +323,14 @@ multiclass VPatIntegerSetCCSDNode_XI_Swappable { foreach vti = AllIntegerVectors in { defvar instruction = !cast(instruction_name#_#kind#_#vti.LMul.MX); - def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1), - (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)), - (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>; - def : Pat<(vti.Mask (setcc (vti.Vector (SplatPatKind xop_kind:$rs2)), - (vti.Vector vti.RegClass:$rs1), invcc)), - (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>; + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1), + (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)), + (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>; + def : Pat<(vti.Mask (setcc (vti.Vector (SplatPatKind xop_kind:$rs2)), + (vti.Vector vti.RegClass:$rs1), invcc)), + (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>; + } } } @@ -329,6 +346,7 @@ multiclass VPatIntegerSetCCSDNode_VIPlus1 { foreach vti = AllIntegerVectors in { defvar instruction = !cast(instruction_name#"_VI_"#vti.LMul.MX); + let Predicates = GetVTypePredicates.Predicates in def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1), (vti.Vector (splatpat_kind simm5:$rs2)), cc)), @@ -341,23 +359,25 @@ multiclass VPatFPSetCCSDNode_VV_VF_FV { foreach fvti = AllFloatVectors in { - def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1), - (fvti.Vector fvti.RegClass:$rs2), - cc)), - (!cast(inst_name#"_VV_"#fvti.LMul.MX) - fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.AVL, fvti.Log2SEW)>; - def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1), - (SplatFPOp fvti.ScalarRegClass:$rs2), - cc)), - (!cast(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) - fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, - fvti.AVL, fvti.Log2SEW)>; - def : Pat<(fvti.Mask (setcc (SplatFPOp fvti.ScalarRegClass:$rs2), - (fvti.Vector fvti.RegClass:$rs1), - cc)), - (!cast(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) - fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, - fvti.AVL, fvti.Log2SEW)>; + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1), + (fvti.Vector fvti.RegClass:$rs2), + cc)), + (!cast(inst_name#"_VV_"#fvti.LMul.MX) + fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.AVL, fvti.Log2SEW)>; + def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1), + (SplatFPOp fvti.ScalarRegClass:$rs2), + cc)), + (!cast(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) + fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, + fvti.AVL, fvti.Log2SEW)>; + def : Pat<(fvti.Mask (setcc (SplatFPOp fvti.ScalarRegClass:$rs2), + (fvti.Vector fvti.RegClass:$rs1), + cc)), + (!cast(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) + fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, + fvti.AVL, fvti.Log2SEW)>; + } } } @@ -367,6 +387,8 @@ multiclass VPatExtendSDNode_V ops, string inst_name, string suffix, defvar vti = vtiTofti.Vti; defvar fti = vtiTofti.Fti; foreach op = ops in + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in def : Pat<(vti.Vector (op (fti.Vector fti.RegClass:$rs2))), (!cast(inst_name#"_"#suffix#"_"#vti.LMul.MX) fti.RegClass:$rs2, fti.AVL, vti.Log2SEW)>; @@ -377,6 +399,8 @@ multiclass VPatConvertI2FPSDNode_V { foreach fvti = AllFloatVectors in { defvar ivti = GetIntVTypeInfo.Vti; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))), (!cast(instruction_name#"_"#fvti.LMul.MX) ivti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; @@ -387,6 +411,8 @@ multiclass VPatConvertFP2ISDNode_V { foreach fvti = AllFloatVectors in { defvar ivti = GetIntVTypeInfo.Vti; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))), (!cast(instruction_name#"_"#ivti.LMul.MX) fvti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>; @@ -398,6 +424,8 @@ multiclass VPatWConvertI2FPSDNode_V.Predicates, + GetVTypePredicates.Predicates) in def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))), (!cast(instruction_name#"_"#ivti.LMul.MX) ivti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>; @@ -409,6 +437,8 @@ multiclass VPatWConvertFP2ISDNode_V.Vti; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))), (!cast(instruction_name#"_"#fvti.LMul.MX) fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; @@ -420,6 +450,8 @@ multiclass VPatNConvertI2FPSDNode_W.Vti; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1))), (!cast(instruction_name#"_"#fvti.LMul.MX) iwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; @@ -431,6 +463,8 @@ multiclass VPatNConvertFP2ISDNode_W.Predicates, + GetVTypePredicates.Predicates) in def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1))), (!cast(instruction_name#"_"#vti.LMul.MX) fwti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; @@ -442,14 +476,17 @@ multiclass VPatWidenBinarySDNode_VV_VX(instruction_name#"_VV_"#vti.LMul.MX) - vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; - def : Pat<(op (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs2))), - (wti.Vector (extop2 (vti.Vector (SplatPat GPR:$rs1))))), - (!cast(instruction_name#"_VX_"#vti.LMul.MX) - vti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in { + def : Pat<(op (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs2))), + (wti.Vector (extop2 (vti.Vector vti.RegClass:$rs1)))), + (!cast(instruction_name#"_VV_"#vti.LMul.MX) + vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; + def : Pat<(op (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs2))), + (wti.Vector (extop2 (vti.Vector (SplatPat GPR:$rs1))))), + (!cast(instruction_name#"_VX_"#vti.LMul.MX) + vti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>; + } } } @@ -458,15 +495,18 @@ multiclass VPatWidenBinarySDNode_WV_WX(instruction_name#"_WV_"#vti.LMul.MX#"_TIED") - wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, - TAIL_AGNOSTIC)>; - def : Pat<(op (wti.Vector wti.RegClass:$rs2), - (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1))))), - (!cast(instruction_name#"_WX_"#vti.LMul.MX) - wti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in { + def : Pat<(op (wti.Vector wti.RegClass:$rs2), + (wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))), + (!cast(instruction_name#"_WV_"#vti.LMul.MX#"_TIED") + wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, + TAIL_AGNOSTIC)>; + def : Pat<(op (wti.Vector wti.RegClass:$rs2), + (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1))))), + (!cast(instruction_name#"_WX_"#vti.LMul.MX) + wti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>; + } } } @@ -479,6 +519,8 @@ multiclass VPatWidenMulAddSDNode_VV.Predicates, + GetVTypePredicates.Predicates) in def : Pat< (add (wti.Vector wti.RegClass:$rd), (mul_oneuse (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs1))), @@ -493,6 +535,8 @@ multiclass VPatWidenMulAddSDNode_VX.Predicates, + GetVTypePredicates.Predicates) in def : Pat< (add (wti.Vector wti.RegClass:$rd), (mul_oneuse (wti.Vector (extop1 (vti.Vector (SplatPat GPR:$rs1)))), @@ -508,28 +552,31 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF { foreach vtiToWti = AllWidenableFloatVectors in { defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; - def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue))), - (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs1), - (vti.Mask true_mask), (XLenVT srcvalue)))), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) - vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; - def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue))), - (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), - (vti.Mask true_mask), (XLenVT srcvalue)))), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; - def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue))), - (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in { + def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue))), + (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs1), + (vti.Mask true_mask), (XLenVT srcvalue)))), + (!cast(instruction_name#"_VV_"#vti.LMul.MX) + vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; + def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue))), + (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), + (vti.Mask true_mask), (XLenVT srcvalue)))), + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; + def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue))), + (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; + } } } @@ -537,23 +584,26 @@ multiclass VPatWidenBinaryFPSDNode_WV_WF { foreach vtiToWti = AllWidenableFloatVectors in { defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; - def : Pat<(op (wti.Vector wti.RegClass:$rs2), - (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs1), - (vti.Mask true_mask), (XLenVT srcvalue)))), - (!cast(instruction_name#"_WV_"#vti.LMul.MX#"_TIED") - wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, - TAIL_AGNOSTIC)>; - def : Pat<(op (wti.Vector wti.RegClass:$rs2), - (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), - (vti.Mask true_mask), (XLenVT srcvalue)))), - (!cast(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) - wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; - def : Pat<(op (wti.Vector wti.RegClass:$rs2), - (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), - (!cast(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) - wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in { + def : Pat<(op (wti.Vector wti.RegClass:$rs2), + (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs1), + (vti.Mask true_mask), (XLenVT srcvalue)))), + (!cast(instruction_name#"_WV_"#vti.LMul.MX#"_TIED") + wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, + TAIL_AGNOSTIC)>; + def : Pat<(op (wti.Vector wti.RegClass:$rs2), + (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), + (vti.Mask true_mask), (XLenVT srcvalue)))), + (!cast(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) + wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; + def : Pat<(op (wti.Vector wti.RegClass:$rs2), + (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), + (!cast(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) + wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; + } } } @@ -566,25 +616,28 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF { foreach vtiToWti = AllWidenableFloatVectors in { defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; - def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs1), - (vti.Mask true_mask), (XLenVT srcvalue))), - (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue))), - (wti.Vector wti.RegClass:$rd)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) - wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fma (wti.Vector (SplatFPOp - (fpext_oneuse vti.ScalarRegClass:$rs1))), - (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue))), - (wti.Vector wti.RegClass:$rd)), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in { + def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs1), + (vti.Mask true_mask), (XLenVT srcvalue))), + (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue))), + (wti.Vector wti.RegClass:$rd)), + (!cast(instruction_name#"_VV_"#vti.LMul.MX) + wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fma (wti.Vector (SplatFPOp + (fpext_oneuse vti.ScalarRegClass:$rs1))), + (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue))), + (wti.Vector wti.RegClass:$rd)), + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + } } } @@ -592,30 +645,33 @@ multiclass VPatWidenFPNegMulAccSDNode_VV_VF { foreach vtiToWti = AllWidenableFloatVectors in { defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; - def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs1), - (vti.Mask true_mask), (XLenVT srcvalue)))), - (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue)), - (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) - wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fma (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)), - (fneg (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue)))), - (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), - (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue)), - (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in { + def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs1), + (vti.Mask true_mask), (XLenVT srcvalue)))), + (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue)), + (fneg wti.RegClass:$rd)), + (!cast(instruction_name#"_VV_"#vti.LMul.MX) + wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fma (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)), + (fneg (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue)))), + (fneg wti.RegClass:$rd)), + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), + (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue)), + (fneg wti.RegClass:$rd)), + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + } } } @@ -623,22 +679,25 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF { foreach vtiToWti = AllWidenableFloatVectors in { defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; - def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs1), - (vti.Mask true_mask), (XLenVT srcvalue))), - (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue)), - (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) - wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))), - (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue)), - (fneg wti.RegClass:$rd)), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in { + def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs1), + (vti.Mask true_mask), (XLenVT srcvalue))), + (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue)), + (fneg wti.RegClass:$rd)), + (!cast(instruction_name#"_VV_"#vti.LMul.MX) + wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))), + (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue)), + (fneg wti.RegClass:$rd)), + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + } } } @@ -646,50 +705,55 @@ multiclass VPatWidenFPNegMulSacSDNode_VV_VF { foreach vtiToWti = AllWidenableFloatVectors in { defvar vti = vtiToWti.Vti; defvar wti = vtiToWti.Wti; - def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs1), - (vti.Mask true_mask), (XLenVT srcvalue)))), - (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue)), - wti.RegClass:$rd), - (!cast(instruction_name#"_VV_"#vti.LMul.MX) - wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))), - (fneg (wti.Vector (riscv_fpextend_vl_oneuse - (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue)))), - wti.RegClass:$rd), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), - (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), - (vti.Mask true_mask), (XLenVT srcvalue)), - wti.RegClass:$rd), - (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in { + def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs1), + (vti.Mask true_mask), (XLenVT srcvalue)))), + (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue)), + wti.RegClass:$rd), + (!cast(instruction_name#"_VV_"#vti.LMul.MX) + wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fma (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1))), + (fneg (wti.Vector (riscv_fpextend_vl_oneuse + (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue)))), + wti.RegClass:$rd), + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fma (fneg (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), + (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), + (vti.Mask true_mask), (XLenVT srcvalue)), + wti.RegClass:$rd), + (!cast(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + } } } multiclass VPatMultiplyAddSDNode_VV_VX { foreach vti = AllIntegerVectors in { defvar suffix = vti.LMul.MX; - // NOTE: We choose VMADD because it has the most commuting freedom. So it - // works best with how TwoAddressInstructionPass tries commuting. - def : Pat<(vti.Vector (op vti.RegClass:$rs2, - (mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))), - (!cast(instruction_name#"_VV_"# suffix) - vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; - // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally - // commutable. - def : Pat<(vti.Vector (op vti.RegClass:$rs2, - (mul_oneuse (SplatPat XLenVT:$rs1), vti.RegClass:$rd))), - (!cast(instruction_name#"_VX_" # suffix) - vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, - vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + let Predicates = GetVTypePredicates.Predicates in { + // NOTE: We choose VMADD because it has the most commuting freedom. So it + // works best with how TwoAddressInstructionPass tries commuting. + def : Pat<(vti.Vector (op vti.RegClass:$rs2, + (mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))), + (!cast(instruction_name#"_VV_"# suffix) + vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally + // commutable. + def : Pat<(vti.Vector (op vti.RegClass:$rs2, + (mul_oneuse (SplatPat XLenVT:$rs1), vti.RegClass:$rd))), + (!cast(instruction_name#"_VX_" # suffix) + vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, + vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; + } } } @@ -697,20 +761,22 @@ multiclass VPatMultiplyAddSDNode_VV_VX { // Patterns. //===----------------------------------------------------------------------===// -let Predicates = [HasVInstructions] in { - // 7.4. Vector Unit-Stride Instructions foreach vti = !listconcat(FractionalGroupIntegerVectors, FractionalGroupFloatVectors) in + let Predicates = GetVTypePredicates.Predicates in defm : VPatUSLoadStoreSDNode; foreach vti = [VI8M1, VI16M1, VI32M1, VI64M1, VF16M1, VF32M1, VF64M1] in + let Predicates = GetVTypePredicates.Predicates in defm : VPatUSLoadStoreWholeVRSDNode; foreach vti = !listconcat(GroupIntegerVectors, GroupFloatVectors) in + let Predicates = GetVTypePredicates.Predicates in defm : VPatUSLoadStoreWholeVRSDNode; foreach mti = AllMasks in + let Predicates = [HasVInstructions] in defm : VPatUSLoadStoreMaskSDNode; // 11. Vector Integer Arithmetic Instructions @@ -721,14 +787,16 @@ defm : VPatBinarySDNode_VV_VX; // Handle VRSUB specially since it's the only integer binary op with reversed // pattern operands foreach vti = AllIntegerVectors in { - def : Pat<(sub (vti.Vector (SplatPat GPR:$rs2)), - (vti.Vector vti.RegClass:$rs1)), - (!cast("PseudoVRSUB_VX_"# vti.LMul.MX) - vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.Log2SEW)>; - def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)), - (vti.Vector vti.RegClass:$rs1)), - (!cast("PseudoVRSUB_VI_"# vti.LMul.MX) - vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>; + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(sub (vti.Vector (SplatPat GPR:$rs2)), + (vti.Vector vti.RegClass:$rs1)), + (!cast("PseudoVRSUB_VX_"# vti.LMul.MX) + vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.Log2SEW)>; + def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)), + (vti.Vector vti.RegClass:$rs1)), + (!cast("PseudoVRSUB_VI_"# vti.LMul.MX) + vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>; + } } // 11.2. Vector Widening Integer Add and Subtract @@ -766,6 +834,7 @@ defm : VPatBinarySDNode_VV_VX_VI; foreach vti = AllIntegerVectors in { // Emit shift by 1 as an add since it might be faster. + let Predicates = GetVTypePredicates.Predicates in def : Pat<(shl (vti.Vector vti.RegClass:$rs1), (vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)))), (!cast("PseudoVADD_VV_"# vti.LMul.MX) @@ -816,8 +885,14 @@ defm : VPatBinarySDNode_VV_VX; // 11.10. Vector Single-Width Integer Multiply Instructions defm : VPatBinarySDNode_VV_VX; -defm : VPatBinarySDNode_VV_VX; -defm : VPatBinarySDNode_VV_VX; + +defm : VPatBinarySDNode_VV_VX; +defm : VPatBinarySDNode_VV_VX; + +let Predicates = [HasVInstructionsFullMultiply] in { + defm : VPatBinarySDNode_VV_VX; + defm : VPatBinarySDNode_VV_VX; +} // 11.11. Vector Integer Divide Instructions defm : VPatBinarySDNode_VV_VX_E; @@ -854,21 +929,23 @@ defm : VPatWidenMulAddSDNode_VX; // 11.15. Vector Integer Merge Instructions foreach vti = AllIntegerVectors in { - def : Pat<(vti.Vector (vselect (vti.Mask V0), vti.RegClass:$rs1, - vti.RegClass:$rs2)), - (!cast("PseudoVMERGE_VVM_"#vti.LMul.MX) - vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), - vti.AVL, vti.Log2SEW)>; - - def : Pat<(vti.Vector (vselect (vti.Mask V0), (SplatPat XLenVT:$rs1), - vti.RegClass:$rs2)), - (!cast("PseudoVMERGE_VXM_"#vti.LMul.MX) - vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), vti.AVL, vti.Log2SEW)>; - - def : Pat<(vti.Vector (vselect (vti.Mask V0), (SplatPat_simm5 simm5:$rs1), - vti.RegClass:$rs2)), - (!cast("PseudoVMERGE_VIM_"#vti.LMul.MX) - vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), vti.AVL, vti.Log2SEW)>; + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(vti.Vector (vselect (vti.Mask V0), vti.RegClass:$rs1, + vti.RegClass:$rs2)), + (!cast("PseudoVMERGE_VVM_"#vti.LMul.MX) + vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), + vti.AVL, vti.Log2SEW)>; + + def : Pat<(vti.Vector (vselect (vti.Mask V0), (SplatPat XLenVT:$rs1), + vti.RegClass:$rs2)), + (!cast("PseudoVMERGE_VXM_"#vti.LMul.MX) + vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), vti.AVL, vti.Log2SEW)>; + + def : Pat<(vti.Vector (vselect (vti.Mask V0), (SplatPat_simm5 simm5:$rs1), + vti.RegClass:$rs2)), + (!cast("PseudoVMERGE_VIM_"#vti.LMul.MX) + vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), vti.AVL, vti.Log2SEW)>; + } } // 12. Vector Fixed-Point Arithmetic Instructions @@ -883,45 +960,43 @@ defm : VPatBinarySDNode_VV_VX; // 15.1. Vector Mask-Register Logical Instructions foreach mti = AllMasks in { - def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)), - (!cast("PseudoVMAND_MM_"#mti.LMul.MX) - VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; - def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)), - (!cast("PseudoVMOR_MM_"#mti.LMul.MX) - VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; - def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)), - (!cast("PseudoVMXOR_MM_"#mti.LMul.MX) - VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; - - def : Pat<(mti.Mask (rvv_vnot (and VR:$rs1, VR:$rs2))), - (!cast("PseudoVMNAND_MM_"#mti.LMul.MX) - VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; - def : Pat<(mti.Mask (rvv_vnot (or VR:$rs1, VR:$rs2))), - (!cast("PseudoVMNOR_MM_"#mti.LMul.MX) - VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; - def : Pat<(mti.Mask (rvv_vnot (xor VR:$rs1, VR:$rs2))), - (!cast("PseudoVMXNOR_MM_"#mti.LMul.MX) - VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; - - def : Pat<(mti.Mask (and VR:$rs1, (rvv_vnot VR:$rs2))), - (!cast("PseudoVMANDN_MM_"#mti.LMul.MX) - VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; - def : Pat<(mti.Mask (or VR:$rs1, (rvv_vnot VR:$rs2))), - (!cast("PseudoVMORN_MM_"#mti.LMul.MX) - VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; - - // Handle rvv_vnot the same as the vmnot.m pseudoinstruction. - def : Pat<(mti.Mask (rvv_vnot VR:$rs)), - (!cast("PseudoVMNAND_MM_"#mti.LMul.MX) - VR:$rs, VR:$rs, mti.AVL, mti.Log2SEW)>; + let Predicates = [HasVInstructions] in { + def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)), + (!cast("PseudoVMAND_MM_"#mti.LMul.MX) + VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; + def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)), + (!cast("PseudoVMOR_MM_"#mti.LMul.MX) + VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; + def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)), + (!cast("PseudoVMXOR_MM_"#mti.LMul.MX) + VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; + + def : Pat<(mti.Mask (rvv_vnot (and VR:$rs1, VR:$rs2))), + (!cast("PseudoVMNAND_MM_"#mti.LMul.MX) + VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; + def : Pat<(mti.Mask (rvv_vnot (or VR:$rs1, VR:$rs2))), + (!cast("PseudoVMNOR_MM_"#mti.LMul.MX) + VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; + def : Pat<(mti.Mask (rvv_vnot (xor VR:$rs1, VR:$rs2))), + (!cast("PseudoVMXNOR_MM_"#mti.LMul.MX) + VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; + + def : Pat<(mti.Mask (and VR:$rs1, (rvv_vnot VR:$rs2))), + (!cast("PseudoVMANDN_MM_"#mti.LMul.MX) + VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; + def : Pat<(mti.Mask (or VR:$rs1, (rvv_vnot VR:$rs2))), + (!cast("PseudoVMORN_MM_"#mti.LMul.MX) + VR:$rs1, VR:$rs2, mti.AVL, mti.Log2SEW)>; + + // Handle rvv_vnot the same as the vmnot.m pseudoinstruction. + def : Pat<(mti.Mask (rvv_vnot VR:$rs)), + (!cast("PseudoVMNAND_MM_"#mti.LMul.MX) + VR:$rs, VR:$rs, mti.AVL, mti.Log2SEW)>; + } } -} // Predicates = [HasVInstructions] - // 13. Vector Floating-Point Instructions -let Predicates = [HasVInstructionsAnyF] in { - // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions defm : VPatBinaryFPSDNode_VV_VF; defm : VPatBinaryFPSDNode_VV_VF; @@ -944,62 +1019,64 @@ foreach fvti = AllFloatVectors in { // NOTE: We choose VFMADD because it has the most commuting freedom. So it // works best with how TwoAddressInstructionPass tries commuting. defvar suffix = fvti.LMul.MX; - def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd, - fvti.RegClass:$rs2)), - (!cast("PseudoVFMADD_VV_"# suffix) - fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd, - (fneg fvti.RegClass:$rs2))), - (!cast("PseudoVFMSUB_VV_"# suffix) - fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd, - (fneg fvti.RegClass:$rs2))), - (!cast("PseudoVFNMADD_VV_"# suffix) - fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd, - fvti.RegClass:$rs2)), - (!cast("PseudoVFNMSUB_VV_"# suffix) - fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; - - // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally - // commutable. - def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), - fvti.RegClass:$rd, fvti.RegClass:$rs2)), - (!cast("PseudoVFMADD_V" # fvti.ScalarSuffix # "_" # suffix) - fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), - fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), - (!cast("PseudoVFMSUB_V" # fvti.ScalarSuffix # "_" # suffix) - fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; - - def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), - (fneg fvti.RegClass:$rd), (fneg fvti.RegClass:$rs2))), - (!cast("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix) - fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), - (fneg fvti.RegClass:$rd), fvti.RegClass:$rs2)), - (!cast("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix) - fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; - - // The splat might be negated. - def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)), - fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), - (!cast("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix) - fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; - def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)), - fvti.RegClass:$rd, fvti.RegClass:$rs2)), - (!cast("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix) - fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, - fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd, + fvti.RegClass:$rs2)), + (!cast("PseudoVFMADD_VV_"# suffix) + fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd, + (fneg fvti.RegClass:$rs2))), + (!cast("PseudoVFMSUB_VV_"# suffix) + fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd, + (fneg fvti.RegClass:$rs2))), + (!cast("PseudoVFNMADD_VV_"# suffix) + fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd, + fvti.RegClass:$rs2)), + (!cast("PseudoVFNMSUB_VV_"# suffix) + fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + + // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally + // commutable. + def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), + fvti.RegClass:$rd, fvti.RegClass:$rs2)), + (!cast("PseudoVFMADD_V" # fvti.ScalarSuffix # "_" # suffix) + fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), + fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), + (!cast("PseudoVFMSUB_V" # fvti.ScalarSuffix # "_" # suffix) + fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + + def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), + (fneg fvti.RegClass:$rd), (fneg fvti.RegClass:$rs2))), + (!cast("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix) + fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), + (fneg fvti.RegClass:$rd), fvti.RegClass:$rs2)), + (!cast("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix) + fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + + // The splat might be negated. + def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)), + fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), + (!cast("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix) + fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)), + fvti.RegClass:$rd, fvti.RegClass:$rs2)), + (!cast("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix) + fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, + fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; + } } // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions @@ -1009,37 +1086,39 @@ defm : VPatWidenFPMulSacSDNode_VV_VF<"PseudoVFWMSAC">; defm : VPatWidenFPNegMulSacSDNode_VV_VF<"PseudoVFWNMSAC">; foreach vti = AllFloatVectors in { - // 13.8. Vector Floating-Point Square-Root Instruction - def : Pat<(any_fsqrt (vti.Vector vti.RegClass:$rs2)), - (!cast("PseudoVFSQRT_V_"# vti.LMul.MX#"_E"#vti.SEW) - vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; - - // 13.12. Vector Floating-Point Sign-Injection Instructions - def : Pat<(fabs (vti.Vector vti.RegClass:$rs)), - (!cast("PseudoVFSGNJX_VV_"# vti.LMul.MX) - vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>; - // Handle fneg with VFSGNJN using the same input for both operands. - def : Pat<(fneg (vti.Vector vti.RegClass:$rs)), - (!cast("PseudoVFSGNJN_VV_"# vti.LMul.MX) - vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>; - - def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), - (vti.Vector vti.RegClass:$rs2))), - (!cast("PseudoVFSGNJ_VV_"# vti.LMul.MX) - vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; - def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), - (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs2)))), - (!cast("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>; - - def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), - (vti.Vector (fneg vti.RegClass:$rs2)))), - (!cast("PseudoVFSGNJN_VV_"# vti.LMul.MX) - vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; - def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), - (vti.Vector (fneg (SplatFPOp vti.ScalarRegClass:$rs2))))), - (!cast("PseudoVFSGNJN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) - vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>; + let Predicates = GetVTypePredicates.Predicates in { + // 13.8. Vector Floating-Point Square-Root Instruction + def : Pat<(any_fsqrt (vti.Vector vti.RegClass:$rs2)), + (!cast("PseudoVFSQRT_V_"# vti.LMul.MX#"_E"#vti.SEW) + vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; + + // 13.12. Vector Floating-Point Sign-Injection Instructions + def : Pat<(fabs (vti.Vector vti.RegClass:$rs)), + (!cast("PseudoVFSGNJX_VV_"# vti.LMul.MX) + vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>; + // Handle fneg with VFSGNJN using the same input for both operands. + def : Pat<(fneg (vti.Vector vti.RegClass:$rs)), + (!cast("PseudoVFSGNJN_VV_"# vti.LMul.MX) + vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>; + + def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), + (vti.Vector vti.RegClass:$rs2))), + (!cast("PseudoVFSGNJ_VV_"# vti.LMul.MX) + vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; + def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), + (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs2)))), + (!cast("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>; + + def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), + (vti.Vector (fneg vti.RegClass:$rs2)))), + (!cast("PseudoVFSGNJN_VV_"# vti.LMul.MX) + vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; + def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), + (vti.Vector (fneg (SplatFPOp vti.ScalarRegClass:$rs2))))), + (!cast("PseudoVFSGNJN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) + vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>; + } } // 13.11. Vector Floating-Point MIN/MAX Instructions @@ -1063,25 +1142,27 @@ defm : VPatFPSetCCSDNode_VV_VF_FV; // 11.15. Vector Integer Merge Instructions // 13.15. Vector Floating-Point Merge Instruction foreach fvti = AllFloatVectors in { - def : Pat<(fvti.Vector (vselect (fvti.Mask V0), fvti.RegClass:$rs1, - fvti.RegClass:$rs2)), - (!cast("PseudoVMERGE_VVM_"#fvti.LMul.MX) - fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), - fvti.AVL, fvti.Log2SEW)>; - - def : Pat<(fvti.Vector (vselect (fvti.Mask V0), - (SplatFPOp fvti.ScalarRegClass:$rs1), - fvti.RegClass:$rs2)), - (!cast("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) - fvti.RegClass:$rs2, - (fvti.Scalar fvti.ScalarRegClass:$rs1), - (fvti.Mask V0), fvti.AVL, fvti.Log2SEW)>; - - def : Pat<(fvti.Vector (vselect (fvti.Mask V0), - (SplatFPOp (fvti.Scalar fpimm0)), - fvti.RegClass:$rs2)), - (!cast("PseudoVMERGE_VIM_"#fvti.LMul.MX) - fvti.RegClass:$rs2, 0, (fvti.Mask V0), fvti.AVL, fvti.Log2SEW)>; + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(fvti.Vector (vselect (fvti.Mask V0), fvti.RegClass:$rs1, + fvti.RegClass:$rs2)), + (!cast("PseudoVMERGE_VVM_"#fvti.LMul.MX) + fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), + fvti.AVL, fvti.Log2SEW)>; + + def : Pat<(fvti.Vector (vselect (fvti.Mask V0), + (SplatFPOp fvti.ScalarRegClass:$rs1), + fvti.RegClass:$rs2)), + (!cast("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) + fvti.RegClass:$rs2, + (fvti.Scalar fvti.ScalarRegClass:$rs1), + (fvti.Mask V0), fvti.AVL, fvti.Log2SEW)>; + + def : Pat<(fvti.Vector (vselect (fvti.Mask V0), + (SplatFPOp (fvti.Scalar fpimm0)), + fvti.RegClass:$rs2)), + (!cast("PseudoVMERGE_VIM_"#fvti.LMul.MX) + fvti.RegClass:$rs2, 0, (fvti.Mask V0), fvti.AVL, fvti.Log2SEW)>; + } } // 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions @@ -1104,33 +1185,33 @@ defm : VPatNConvertI2FPSDNode_W; foreach fvtiToFWti = AllWidenableFloatVectors in { defvar fvti = fvtiToFWti.Vti; defvar fwti = fvtiToFWti.Wti; + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypePredicates.Predicates) in def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))), (!cast("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX) fwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; } -} // Predicates = [HasVInstructionsAnyF] //===----------------------------------------------------------------------===// // Vector Splats //===----------------------------------------------------------------------===// -let Predicates = [HasVInstructionsAnyF] in { foreach fvti = AllFloatVectors in { - def : Pat<(fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), - (!cast("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) - (fvti.Scalar fvti.ScalarRegClass:$rs1), - fvti.AVL, fvti.Log2SEW)>; - - def : Pat<(fvti.Vector (SplatFPOp (fvti.Scalar fpimm0))), - (!cast("PseudoVMV_V_I_"#fvti.LMul.MX) - 0, fvti.AVL, fvti.Log2SEW)>; + let Predicates = GetVTypePredicates.Predicates in { + def : Pat<(fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), + (!cast("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) + (fvti.Scalar fvti.ScalarRegClass:$rs1), + fvti.AVL, fvti.Log2SEW)>; + + def : Pat<(fvti.Vector (SplatFPOp (fvti.Scalar fpimm0))), + (!cast("PseudoVMV_V_I_"#fvti.LMul.MX) + 0, fvti.AVL, fvti.Log2SEW)>; + } } -} // Predicates = [HasVInstructionsAnyF] //===----------------------------------------------------------------------===// // Vector Element Extracts //===----------------------------------------------------------------------===// -let Predicates = [HasVInstructionsAnyF] in foreach vti = AllFloatVectors in { defvar vmv_f_s_inst = !cast(!strconcat("PseudoVFMV_", vti.ScalarSuffix, @@ -1138,6 +1219,7 @@ foreach vti = AllFloatVectors in { // Only pattern-match extract-element operations where the index is 0. Any // other index will have been custom-lowered to slide the vector correctly // into place. + let Predicates = GetVTypePredicates.Predicates in def : Pat<(vti.Scalar (extractelt (vti.Vector vti.RegClass:$rs2), 0)), (vmv_f_s_inst vti.RegClass:$rs2, vti.Log2SEW)>; } -- cgit v1.2.1