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| author | Mike Pall <mike> | 2012-03-30 01:34:17 +0200 |
|---|---|---|
| committer | Mike Pall <mike> | 2012-03-30 01:34:17 +0200 |
| commit | 2225c9aafc9245e12b22d34b68be8017c42febd8 (patch) | |
| tree | 7bbd093737535404e793384014c1f7d11df5e542 | |
| parent | aaaf0e0f5fe573e7c089ece1bd491a8f8b8b3e9a (diff) | |
| download | luajit2-2225c9aafc9245e12b22d34b68be8017c42febd8.tar.gz | |
MIPS: Add MIPS32R2 compile-time/runtime CPU detection.
| -rw-r--r-- | src/lib_jit.c | 16 | ||||
| -rw-r--r-- | src/lj_jit.h | 6 |
2 files changed, 21 insertions, 1 deletions
diff --git a/src/lib_jit.c b/src/lib_jit.c index 05a79d51..7d5e0aef 100644 --- a/src/lib_jit.c +++ b/src/lib_jit.c @@ -615,7 +615,21 @@ static uint32_t jit_cpudetect(lua_State *L) #elif LJ_TARGET_PPC || LJ_TARGET_PPCSPE /* Nothing to do. */ #elif LJ_TARGET_MIPS - /* NYI */ +#if LJ_HASJIT + /* Compile-time MIPS CPU detection. */ +#if _MIPS_ARCH_MIPS32R2 + flags |= JIT_F_MIPS32R2; +#endif + /* Runtime MIPS CPU detection. */ +#if defined(__GNUC__) + if (!(flags & JIT_F_MIPS32R2)) { + int x; + /* On MIPS32R1 rotr is treated as srl. rotr r2,r2,1 -> srl r2,r2,1. */ + __asm__("li $2, 1\n\t.long 0x00221042\n\tmove %0, $2" : "=r"(x) : : "$2"); + if (x) flags |= JIT_F_MIPS32R2; /* Either 0x80000000 (R2) or 0 (R1). */ + } +#endif +#endif #else #error "Missing CPU detection for this architecture" #endif diff --git a/src/lj_jit.h b/src/lj_jit.h index 1033e792..dd0c08d8 100644 --- a/src/lj_jit.h +++ b/src/lj_jit.h @@ -34,6 +34,12 @@ /* Names for the CPU-specific flags. Must match the order above. */ #define JIT_F_CPU_FIRST JIT_F_ARMV6 #define JIT_F_CPUSTRING "\5ARMv6\7ARMv6T2\5ARMv7" +#elif LJ_TARGET_MIPS +#define JIT_F_MIPS32R2 0x00000010 + +/* Names for the CPU-specific flags. Must match the order above. */ +#define JIT_F_CPU_FIRST JIT_F_MIPS32R2 +#define JIT_F_CPUSTRING "\010MIPS32R2" #else #define JIT_F_CPU_FIRST 0 #define JIT_F_CPUSTRING "" |