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| author | alexfanqi <alex.fan.q@gmail.com> | 2022-01-04 13:59:59 +1100 |
|---|---|---|
| committer | Daniel Black <daniel@mariadb.org> | 2022-01-06 10:36:55 +1100 |
| commit | d18f6f263119b9d2f533373fb5130d9043a8f904 (patch) | |
| tree | 2d183b30f52c02963855a7257778450cc7ffb765 /mysys/my_rdtsc.c | |
| parent | b0d632a8409364e5a539a75e06fb994037ebde36 (diff) | |
| download | mariadb-git-d18f6f263119b9d2f533373fb5130d9043a8f904.tar.gz | |
MDEV-27429: Support RISC-V cycle timer
Adapted from https://github.com/google/benchmark/pull/833
authored by Sam Elliot at lowRISC.
This requires the RISCV kernel to set the CY bit of the mcountern register
which is done on Linux, but documenting here in case another OS hits
a SIGILL here.
When CY bit of the mcounteren register is unset, reading the cycle register
will cause illegal instruction exception in the next privilege level ( user
mode or supervisor mode ). See the privileged isa manual section 3.1.11 in
https://github.com/riscv/riscv-isa-manual/releases/latest
Diffstat (limited to 'mysys/my_rdtsc.c')
| -rw-r--r-- | mysys/my_rdtsc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/mysys/my_rdtsc.c b/mysys/my_rdtsc.c index 1503a5db442..ffd816024e5 100644 --- a/mysys/my_rdtsc.c +++ b/mysys/my_rdtsc.c @@ -384,6 +384,8 @@ void my_timer_init(MY_TIMER_INFO *mti) mti->cycles.routine= MY_TIMER_ROUTINE_ASM_S390; #elif defined(__GNUC__) && defined (__aarch64__) mti->cycles.routine= MY_TIMER_ROUTINE_AARCH64; +#elif defined(__GNUC__) && defined (__riscv) + mti->cycles.routine= MY_TIMER_ROUTINE_RISCV; #elif defined(HAVE_SYS_TIMES_H) && defined(HAVE_GETHRTIME) mti->cycles.routine= MY_TIMER_ROUTINE_GETHRTIME; #else |