MDEV-19845: Adjust for Skylake based on benchmarks

Even though the PAUSE instruction latency was increased from
about 10 to 140 clock cycles in the Intel Skylake microarchitecture,
it seems to be optimal to reduce the amount of subsequently executed
PAUSE instructions not to 1/14, but to 1/2.

1 files changed, 8 insertions, 3 deletions

diff --git a/mysys/my_cpu.c b/mysys/my_cpu.c
index 9434bceac41..3b0ef08a326 100644
--- a/mysys/my_cpu.c
+++ b/mysys/my_cpu.c
@@ -72,8 +72,13 @@ internally invokes rdtsc. */
   that. In some AMD processors, the PAUSE instruction could take 40 or
   50 cycles. Let us use a shorter delay multiplier for them as well.
 
-  The 1/10 scaling factor (200/20) was derived experimentally by
-  Mikhail Sinyavin from Intel.
+  The 1/2 scaling factor (200/100) was derived experimentally by
+  Steve Shaw from Intel and Sergey Vojtovich from MariaDB Foundation.
+  In an earlier experiment on MySQL code base, a 1/10 scaling factor
+  (200/20) seemed to work best.
+
+  The basic idea of the detection algorithm (run 16 PAUSE instructions
+  between RDTSC) was suggested by Mikhail Sinyavin from Intel.
 */
 void my_cpu_init(void)
 {
@@ -84,6 +89,6 @@ void my_cpu_init(void)
   PAUSE16;
   t2= my_timer_cycles();
   if (t2 - t1 > 30 * 16 && t1 - t0 > 30 * 16)
-    my_cpu_relax_multiplier= 20;
+    my_cpu_relax_multiplier= 100;
 }
 #endif