diff options
Diffstat (limited to 'include/atomic')
| -rw-r--r-- | include/atomic/nolock.h | 42 | ||||
| -rw-r--r-- | include/atomic/rwlock.h | 48 | ||||
| -rw-r--r-- | include/atomic/x86-gcc.h | 58 | ||||
| -rw-r--r-- | include/atomic/x86-msvc.h | 96 |
4 files changed, 244 insertions, 0 deletions
diff --git a/include/atomic/nolock.h b/include/atomic/nolock.h new file mode 100644 index 00000000000..f15c8b13b7f --- /dev/null +++ b/include/atomic/nolock.h @@ -0,0 +1,42 @@ +/* Copyright (C) 2006 MySQL AB + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +#if defined(__i386__) || defined(_M_IX86) + +#ifdef MY_ATOMIC_MODE_DUMMY +# define LOCK "" +#else +# define LOCK "lock" +#endif + +#ifdef __GNUC__ +#include "x86-gcc.h" +#elif defined(_MSC_VER) +#include "x86-msvc.h" +#endif +#endif + +#ifdef make_atomic_cas_body + +typedef struct { } my_atomic_rwlock_t; +#define my_atomic_rwlock_destroy(name) +#define my_atomic_rwlock_init(name) +#define my_atomic_rwlock_rdlock(name) +#define my_atomic_rwlock_wrlock(name) +#define my_atomic_rwlock_rdunlock(name) +#define my_atomic_rwlock_wrunlock(name) + +#endif + diff --git a/include/atomic/rwlock.h b/include/atomic/rwlock.h new file mode 100644 index 00000000000..18b77e93d80 --- /dev/null +++ b/include/atomic/rwlock.h @@ -0,0 +1,48 @@ +/* Copyright (C) 2006 MySQL AB + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +typedef struct {pthread_rwlock_t rw;} my_atomic_rwlock_t; + +#ifdef MY_ATOMIC_MODE_DUMMY +/* + the following can never be enabled by ./configure, one need to put #define in + a source to trigger the following warning. The resulting code will be broken, + it only makes sense to do it to see now test_atomic detects broken + implementations (another way is to run a UP build on an SMP box). +*/ +#warning MY_ATOMIC_MODE_DUMMY and MY_ATOMIC_MODE_RWLOCKS are incompatible +#define my_atomic_rwlock_destroy(name) +#define my_atomic_rwlock_init(name) +#define my_atomic_rwlock_rdlock(name) +#define my_atomic_rwlock_wrlock(name) +#define my_atomic_rwlock_rdunlock(name) +#define my_atomic_rwlock_wrunlock(name) +#define MY_ATOMIC_MODE "dummy (non-atomic)" +#else +#define my_atomic_rwlock_destroy(name) pthread_rwlock_destroy(& (name)->rw) +#define my_atomic_rwlock_init(name) pthread_rwlock_init(& (name)->rw, 0) +#define my_atomic_rwlock_rdlock(name) pthread_rwlock_rdlock(& (name)->rw) +#define my_atomic_rwlock_wrlock(name) pthread_rwlock_wrlock(& (name)->rw) +#define my_atomic_rwlock_rdunlock(name) pthread_rwlock_unlock(& (name)->rw) +#define my_atomic_rwlock_wrunlock(name) pthread_rwlock_unlock(& (name)->rw) +#define MY_ATOMIC_MODE "rwlocks" +#endif + +#define make_atomic_add_body(S) int ## S sav; sav= *a; *a+= v; v=sav; +#define make_atomic_swap_body(S) int ## S sav; sav= *a; *a= v; v=sav; +#define make_atomic_cas_body(S) if ((ret= (*a == *cmp))) *a= set; else *cmp=*a; +#define make_atomic_load_body(S) ret= *a; +#define make_atomic_store_body(S) *a= v; + diff --git a/include/atomic/x86-gcc.h b/include/atomic/x86-gcc.h new file mode 100644 index 00000000000..d79dadbf05e --- /dev/null +++ b/include/atomic/x86-gcc.h @@ -0,0 +1,58 @@ +/* Copyright (C) 2006 MySQL AB + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/* + XXX 64-bit atomic operations can be implemented using + cmpxchg8b, if necessary. Though I've heard that not all 64-bit + architectures support double-word (128-bit) cas. +*/ + +#ifdef MY_ATOMIC_NO_XADD +#define MY_ATOMIC_MODE "gcc-x86" LOCK "-no-xadd" +#else +#define MY_ATOMIC_MODE "gcc-x86" LOCK +#endif + +/* fix -ansi errors while maintaining readability */ +#ifndef asm +#define asm __asm__ +#endif + +#ifndef MY_ATOMIC_NO_XADD +#define make_atomic_add_body(S) \ + asm volatile (LOCK "; xadd %0, %1;" : "+r" (v) , "+m" (*a)) +#endif +#define make_atomic_swap_body(S) \ + asm volatile ("; xchg %0, %1;" : "+r" (v) , "+m" (*a)) +#define make_atomic_cas_body(S) \ + asm volatile (LOCK "; cmpxchg %3, %0; setz %2;" \ + : "+m" (*a), "+a" (*cmp), "=q" (ret): "r" (set)) + +#ifdef MY_ATOMIC_MODE_DUMMY +#define make_atomic_load_body(S) ret=*a +#define make_atomic_store_body(S) *a=v +#else +/* + Actually 32-bit reads/writes are always atomic on x86 + But we add LOCK here anyway to force memory barriers +*/ +#define make_atomic_load_body(S) \ + ret=0; \ + asm volatile (LOCK "; cmpxchg %2, %0" \ + : "+m" (*a), "+a" (ret): "r" (ret)) +#define make_atomic_store_body(S) \ + asm volatile ("; xchg %0, %1;" : "+m" (*a) : "r" (v)) +#endif + diff --git a/include/atomic/x86-msvc.h b/include/atomic/x86-msvc.h new file mode 100644 index 00000000000..c4885bb8451 --- /dev/null +++ b/include/atomic/x86-msvc.h @@ -0,0 +1,96 @@ +/* Copyright (C) 2006 MySQL AB + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; version 2 of the License. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/* + XXX 64-bit atomic operations can be implemented using + cmpxchg8b, if necessary +*/ + +// Would it be better to use intrinsics ? +// (InterlockedCompareExchange, InterlockedCompareExchange16 +// InterlockedExchangeAdd, InterlockedExchange) + +#ifndef _atomic_h_cleanup_ +#define _atomic_h_cleanup_ "atomic/x86-msvc.h" + +#define MY_ATOMIC_MODE "msvc-x86" LOCK + +#define make_atomic_add_body(S) \ + _asm { \ + _asm mov reg_ ## S, v \ + _asm LOCK xadd *a, reg_ ## S \ + _asm movzx v, reg_ ## S \ + } +#define make_atomic_cas_body(S) \ + _asm { \ + _asm mov areg_ ## S, *cmp \ + _asm mov reg2_ ## S, set \ + _asm LOCK cmpxchg *a, reg2_ ## S \ + _asm mov *cmp, areg_ ## S \ + _asm setz al \ + _asm movzx ret, al \ + } +#define make_atomic_swap_body(S) \ + _asm { \ + _asm mov reg_ ## S, v \ + _asm xchg *a, reg_ ## S \ + _asm mov v, reg_ ## S \ + } + +#ifdef MY_ATOMIC_MODE_DUMMY +#define make_atomic_load_body(S) ret=*a +#define make_atomic_store_body(S) *a=v +#else +/* + Actually 32-bit reads/writes are always atomic on x86 + But we add LOCK here anyway to force memory barriers +*/ +#define make_atomic_load_body(S) \ + _asm { \ + _asm mov areg_ ## S, 0 \ + _asm mov reg2_ ## S, areg_ ## S \ + _asm LOCK cmpxchg *a, reg2_ ## S \ + _asm mov ret, areg_ ## S \ + } +#define make_atomic_store_body(S) \ + _asm { \ + _asm mov reg_ ## S, v \ + _asm xchg *a, reg_ ## S \ + } +#endif + +#define reg_8 al +#define reg_16 ax +#define reg_32 eax +#define areg_8 al +#define areg_16 ax +#define areg_32 eax +#define reg2_8 bl +#define reg2_16 bx +#define reg2_32 ebx + +#else /* cleanup */ + +#undef reg_8 +#undef reg_16 +#undef reg_32 +#undef areg_8 +#undef areg_16 +#undef areg_32 +#undef reg2_8 +#undef reg2_16 +#undef reg2_32 +#endif + |