diff options
| author | Nanley Chery <nanley.g.chery@intel.com> | 2022-08-01 14:13:46 -0700 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2022-08-11 09:51:41 -0700 |
| commit | 2a653b2f6f755c4451f52b1b4e795156838f4008 (patch) | |
| tree | 309d6e0f2b753a8a759802ff3336b7f1ec1b822e | |
| parent | 687324893dce5ba7af4dcbf4c79f53bd0f522a81 (diff) | |
| download | mesa-2a653b2f6f755c4451f52b1b4e795156838f4008.tar.gz | |
iris: Make the D16 reg mode single-sampled
Wa_14010455700 is dependent on the format and sample count, but our
code to track whether or not it had been applied was only dependent on
the format.
As a result, we failed to enable the workaround when an app used a D16
2xMSAA buffer, then a D16 1xMSAA buffer right afterwards.
Make the workaround tracking code sample-dependent to fix this.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17859>
(cherry picked from commit a75cd15b94d909417c70612a493bcde9964a1284)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 16 |
2 files changed, 10 insertions, 8 deletions
diff --git a/.pick_status.json b/.pick_status.json index 42b5db50407..7afdd61cb40 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -3442,7 +3442,7 @@ "description": "iris: Make the D16 reg mode single-sampled", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null }, diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index bfa1bb18356..1af9dafd418 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1219,7 +1219,7 @@ struct iris_depth_buffer_state { #if GFX_VERx10 == 120 enum iris_depth_reg_mode { IRIS_DEPTH_REG_MODE_HW_DEFAULT = 0, - IRIS_DEPTH_REG_MODE_D16, + IRIS_DEPTH_REG_MODE_D16_1X_MSAA, IRIS_DEPTH_REG_MODE_UNKNOWN, }; #endif @@ -5737,15 +5737,16 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice, const struct isl_surf *surf) { #if GFX_VERx10 == 120 - const bool fmt_is_d16 = surf->format == ISL_FORMAT_R16_UNORM; + const bool is_d16_1x_msaa = surf->format == ISL_FORMAT_R16_UNORM && + surf->samples == 1; switch (ice->state.genx->depth_reg_mode) { case IRIS_DEPTH_REG_MODE_HW_DEFAULT: - if (!fmt_is_d16) + if (!is_d16_1x_msaa) return; break; - case IRIS_DEPTH_REG_MODE_D16: - if (fmt_is_d16) + case IRIS_DEPTH_REG_MODE_D16_1X_MSAA: + if (is_d16_1x_msaa) return; break; case IRIS_DEPTH_REG_MODE_UNKNOWN: @@ -5767,12 +5768,13 @@ genX(emit_depth_state_workarounds)(struct iris_context *ice, * Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA”. */ iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), reg) { - reg.HIZPlaneOptimizationdisablebit = fmt_is_d16 && surf->samples == 1; + reg.HIZPlaneOptimizationdisablebit = is_d16_1x_msaa; reg.HIZPlaneOptimizationdisablebitMask = true; } ice->state.genx->depth_reg_mode = - fmt_is_d16 ? IRIS_DEPTH_REG_MODE_D16 : IRIS_DEPTH_REG_MODE_HW_DEFAULT; + is_d16_1x_msaa ? IRIS_DEPTH_REG_MODE_D16_1X_MSAA : + IRIS_DEPTH_REG_MODE_HW_DEFAULT; #endif } |