diff options
author | Rafael Antognolli <rafael.antognolli@intel.com> | 2019-04-02 17:08:52 -0700 |
---|---|---|
committer | Plamena Manolova <plamena.manolova@intel.com> | 2019-04-29 17:29:53 +0000 |
commit | 50dd2727cf851f9a90adc34b67b7e99a3945b6ff (patch) | |
tree | 5233c1823a843bd7e4c85a2604e94822327e4678 | |
parent | 863627c50e0d384c0f496190391fa2134a6737d5 (diff) | |
download | mesa-50dd2727cf851f9a90adc34b67b7e99a3945b6ff.tar.gz |
intel/blorp: Make blorp update the clear color in gen11.
Hardware docs say that Gen11 requires the use of two MI_ATOMICs of size
QWORD when updating the clear color. The second MI_ATOMIC also needs CS
Stall and Return Data Control set.
v2: Remove include of srgb header (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
-rw-r--r-- | src/intel/blorp/blorp_genX_exec.h | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index c3bf92c9148..76a1208aa66 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -130,12 +130,13 @@ _blorp_combine_address(struct blorp_batch *batch, void *location, _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \ _dst = NULL) -#define blorp_emitn(batch, cmd, n) ({ \ +#define blorp_emitn(batch, cmd, n, ...) ({ \ uint32_t *_dw = blorp_emit_dwords(batch, n); \ if (_dw) { \ struct cmd template = { \ _blorp_cmd_header(cmd), \ .DWordLength = n - _blorp_cmd_length_bias(cmd), \ + __VA_ARGS__ \ }; \ _blorp_cmd_pack(cmd)(batch, _dw, &template); \ } \ @@ -1733,7 +1734,42 @@ blorp_update_clear_color(struct blorp_batch *batch, enum isl_aux_op op) { if (info->clear_color_addr.buffer && op == ISL_AUX_OP_FAST_CLEAR) { -#if GEN_GEN >= 9 +#if GEN_GEN == 11 + blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { + pipe.CommandStreamerStallEnable = true; + } + + /* 2 QWORDS */ + const unsigned inlinedata_dw = 2 * 2; + const unsigned num_dwords = GENX(MI_ATOMIC_length) + inlinedata_dw; + + struct blorp_address clear_addr = info->clear_color_addr; + uint32_t *dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, + .DataSize = MI_ATOMIC_QWORD, + .ATOMICOPCODE = MI_ATOMIC_OP_MOVE8B, + .InlineData = true, + .MemoryAddress = clear_addr); + /* dw starts at dword 1, but we need to fill dwords 3 and 5 */ + dw[2] = info->clear_color.u32[0]; + dw[4] = info->clear_color.u32[1]; + + clear_addr.offset += 8; + dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, + .DataSize = MI_ATOMIC_QWORD, + .ATOMICOPCODE = MI_ATOMIC_OP_MOVE8B, + .CSSTALL = true, + .ReturnDataControl = true, + .InlineData = true, + .MemoryAddress = clear_addr); + /* dw starts at dword 1, but we need to fill dwords 3 and 5 */ + dw[2] = info->clear_color.u32[2]; + dw[4] = info->clear_color.u32[3]; + + blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { + pipe.StateCacheInvalidationEnable = true; + pipe.TextureCacheInvalidationEnable = true; + } +#elif GEN_GEN >= 9 for (int i = 0; i < 4; i++) { blorp_emit(batch, GENX(MI_STORE_DATA_IMM), sdi) { sdi.Address = info->clear_color_addr; |