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| author | Alex Deucher <alexander.deucher@amd.com> | 2012-10-23 11:58:54 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2012-10-26 09:32:55 -0400 |
| commit | d781f0c73cf47aee7f660d9b859a6c473293be62 (patch) | |
| tree | 07b637cf0604fd81b85de3de18f7802d02c76ce3 /src/gallium/drivers/r600/evergreen_state.c | |
| parent | 20d268b3501cd96f6296a1cb05736c2ed751186e (diff) | |
| download | mesa-d781f0c73cf47aee7f660d9b859a6c473293be62.tar.gz | |
r600g: there are 16 const buffer size regs for each shader stage
we were previously only setting 8 of them.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Diffstat (limited to 'src/gallium/drivers/r600/evergreen_state.c')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 0d02d52b1d3..29e6822a4af 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -3011,7 +3011,7 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0); /* to avoid GPU doing any preloading of constant from random address */ - r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8); + r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16); r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */ r600_store_value(cb, 0); r600_store_value(cb, 0); @@ -3020,7 +3020,16 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, 0); r600_store_value(cb, 0); r600_store_value(cb, 0); - r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + + r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16); r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */ r600_store_value(cb, 0); r600_store_value(cb, 0); @@ -3029,6 +3038,14 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, 0); r600_store_value(cb, 0); r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2); r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */ |