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| author | Jordan Justen <jordan.l.justen@intel.com> | 2016-03-24 00:29:50 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2016-03-24 23:49:53 -0700 |
| commit | 7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e (patch) | |
| tree | 98dd079f8fa3411f6f25931679084ae2866a6ea5 /src/intel/genxml/gen75.xml | |
| parent | d353ba8f5fee23e9d9c8165b6cbfaba33e19ace6 (diff) | |
| download | mesa-7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e.tar.gz | |
genxml: Add L3 Cache Control register definitions
Based on intel_reg.h (5912da45a69923afa1b7f2eb5bb371d848813c41)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/intel/genxml/gen75.xml')
| -rw-r--r-- | src/intel/genxml/gen75.xml | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index 94bb64e595e..26c1f9ecdf6 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -2906,4 +2906,30 @@ <field name="SW Tessellation Memory Object Control State" start="40" end="43" type="MEMORY_OBJECT_CONTROL_STATE"/> </instruction> + <register name="L3SQCREG1" length="1" num="0xb010"> + <field name="Convert DC_UC" start="24" end="24" type="uint"/> + <field name="Convert IS_UC" start="25" end="25" type="uint"/> + <field name="Convert C_UC" start="26" end="26" type="uint"/> + <field name="Convert T_UC" start="27" end="27" type="uint"/> + </register> + + <register name="L3CNTLREG2" length="1" num="0xb020"> + <field name="SLM Enable" start="0" end="0" type="uint"/> + <field name="URB Allocation" start="1" end="6" type="uint"/> + <field name="URB Low Bandwidth" start="7" end="7" type="uint"/> + <field name="RO Allocation" start="14" end="19" type="uint"/> + <field name="RO Low Bandwidth" start="20" end="20" type="uint"/> + <field name="DC Allocation" start="21" end="26" type="uint"/> + <field name="DC Low Bandwidth" start="27" end="27" type="uint"/> + </register> + + <register name="L3CNTLREG3" length="1" num="0xb024"> + <field name="IS Allocation" start="1" end="6" type="uint"/> + <field name="IS Low Bandwidth" start="7" end="7" type="uint"/> + <field name="C Allocation" start="8" end="13" type="uint"/> + <field name="C Low Bandwidth" start="14" end="14" type="uint"/> + <field name="T Allocation" start="15" end="20" type="uint"/> + <field name="T Low Bandwidth" start="21" end="21" type="uint"/> + </register> + </genxml> |