From c3884066172d350e80ac8f1f872e591a6d3f9aba Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 24 Oct 2022 21:29:04 +0300 Subject: anv: Reduce RHWO optimization (Wa_1508744258) Implement Wa_1508744258: Disable RHWO by setting 0x7010[14] by default except during resolve pass. Disable the RCC RHWO optimization at all times except when resolving single sampled color surfaces. v2: Move stalling to genX(cmd_buffer_apply_pipe_flushes) for clarity (Mark) Signed-off-by: Lionel Landwerlin Reviewed-by: Mark Janes Reviewed-by: Jordan Justen Cc: mesa-stable (cherry picked from commit ba0336ab3f69f958e4346c1465c2fe0859d4ac59) Part-of: --- src/intel/vulkan/anv_blorp.c | 12 +++++++++++- src/intel/vulkan/anv_private.h | 11 +++++++++++ src/intel/vulkan/genX_cmd_buffer.c | 28 ++++++++++++++++++++++++++++ src/intel/vulkan/genX_state.c | 13 +++++++++++++ 4 files changed, 63 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index 98c59d43899..e19604a98e2 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1968,10 +1968,20 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer, 0, 0, level_width, level_height); break; case ISL_AUX_OP_FULL_RESOLVE: - case ISL_AUX_OP_PARTIAL_RESOLVE: + case ISL_AUX_OP_PARTIAL_RESOLVE: { + /* Wa_1508744258: Enable RHWO optimization for resolves */ + const bool enable_rhwo_opt = cmd_buffer->device->info.verx10 == 120; + + if (enable_rhwo_opt) + cmd_buffer->state.pending_rhwo_optimization_enabled = true; + blorp_ccs_resolve(&batch, &surf, level, base_layer, layer_count, format, ccs_op); + + if (enable_rhwo_opt) + cmd_buffer->state.pending_rhwo_optimization_enabled = false; break; + } case ISL_AUX_OP_AMBIGUATE: for (uint32_t a = 0; a < layer_count; a++) { const uint32_t layer = base_layer + a; diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index f668355b82c..298b9719fcb 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2760,6 +2760,17 @@ struct anv_cmd_state { */ enum anv_depth_reg_mode depth_reg_mode; + /** + * Whether RHWO optimization is enabled (Wa_1508744258). + */ + bool rhwo_optimization_enabled; + + /** + * Pending state of the RHWO optimization, to be applied at the next + * genX(cmd_buffer_apply_pipe_flushes). + */ + bool pending_rhwo_optimization_enabled; + bool conditional_render_enabled; /** diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index e2cc788a283..d3aa211a844 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2325,6 +2325,21 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, void genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) { +#if GFX_VERx10 == 120 + /* If we're changing the state of the RHWO optimization, we need to have + * sb_stall+cs_stall. + */ + const bool rhwo_opt_change = + cmd_buffer->state.rhwo_optimization_enabled != + cmd_buffer->state.pending_rhwo_optimization_enabled; + if (rhwo_opt_change) { + anv_add_pending_pipe_bits(cmd_buffer, + ANV_PIPE_STALL_AT_SCOREBOARD_BIT | + ANV_PIPE_END_OF_PIPE_SYNC_BIT, + "change RHWO optimization"); + } +#endif + enum anv_pipe_bits bits = cmd_buffer->state.pending_pipe_bits; if (unlikely(cmd_buffer->device->physical->always_flush_cache)) @@ -2355,6 +2370,19 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) cmd_buffer->state.current_pipeline, bits); +#if GFX_VERx10 == 120 + /* Wa_1508744258 handling */ + if (rhwo_opt_change) { + anv_batch_write_reg(&cmd_buffer->batch, GENX(COMMON_SLICE_CHICKEN1), c1) { + c1.RCCRHWOOptimizationDisable = + !cmd_buffer->state.pending_rhwo_optimization_enabled; + c1.RCCRHWOOptimizationDisableMask = true; + } + cmd_buffer->state.rhwo_optimization_enabled = + cmd_buffer->state.pending_rhwo_optimization_enabled; + } +#endif + if (trace_flush) { trace_intel_end_stall(&cmd_buffer->trace, bits, anv_pipe_flush_bit_to_ds_stall_flag, NULL); diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index c4323fbb9aa..4d08ddcfff5 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -348,6 +348,19 @@ init_render_queue_state(struct anv_queue *queue) reg.HZDepthTestLEGEOptimizationDisable = true; reg.HZDepthTestLEGEOptimizationDisableMask = true; } + + /* Wa_1508744258 + * + * Disable RHWO by setting 0x7010[14] by default except during resolve + * pass. + * + * We implement global disabling of the optimization here and we toggle it + * in anv_image_ccs_op(). + */ + anv_batch_write_reg(&batch, GENX(COMMON_SLICE_CHICKEN1), c1) { + c1.RCCRHWOOptimizationDisable = true; + c1.RCCRHWOOptimizationDisableMask = true; + } #endif #if GFX_VERx10 < 125 -- cgit v1.2.1