Import wiredtiger: b61aef73ba16cd63a2c6ec9fc46fe582991d7b44 from branch mongodb-master

ref: a248b1755e..b61aef73ba
for: 6.1.0-rc0

WT-9079       All memory barriers on ARM should be DMB instead of DSB

1 files changed, 12 insertions, 6 deletions

diff --git a/src/third_party/wiredtiger/src/include/gcc.h b/src/third_party/wiredtiger/src/include/gcc.h
index 249d0d8bdae..9eb977f02b5 100644
--- a/src/third_party/wiredtiger/src/include/gcc.h
+++ b/src/third_party/wiredtiger/src/include/gcc.h
@@ -227,10 +227,16 @@ WT_ATOMIC_FUNC(size, size_t, size_t *vp, size_t v)
 #define WT_PAUSE() __asm__ volatile("isb" ::: "memory")
 
 /*
- * dmb are chosen here because they are sufficient to guarantee the ordering described above. We
- * don't want to use dsbs because they provide a much stronger guarantee of completion which isn't
- * required. Additionally, dsbs synchronize other system activities such as tlb and cache
- * maintenance instructions which is not required in this case.
+ * ARM offers three barrier types:
+ *   isb - instruction synchronization barrier
+ *   dmb - data memory barrier
+ *   dsb - data synchronization barrier
+ *
+ * To implement memory barriers for WiredTiger, we need at-least the dmb. dmb are sufficient to
+ * guarantee the ordering described above. We don't want to use dsbs because they provide a much
+ * stronger guarantee of completion which isn't required. Additionally, dsbs synchronize other
+ * system activities such as tlb and cache maintenance instructions which is not required in this
+ * case.
  *
  * A shareability domain of inner-shareable is selected because all the entities participating in
  * the ordering requirements are CPUs and ordering with respect to other devices or memory-types
@@ -242,11 +248,11 @@ WT_ATOMIC_FUNC(size, size_t, size_t *vp, size_t v)
     } while (0)
 #define WT_READ_BARRIER()                           \
     do {                                            \
-        __asm__ volatile("dsb ishld" ::: "memory"); \
+        __asm__ volatile("dmb ishld" ::: "memory"); \
     } while (0)
 #define WT_WRITE_BARRIER()                          \
     do {                                            \
-        __asm__ volatile("dsb ishst" ::: "memory"); \
+        __asm__ volatile("dmb ishst" ::: "memory"); \
     } while (0)
 
 #elif defined(__s390x__)