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| author | Cyrill Gorcunov <gorcunov@gmail.com> | 2012-11-27 15:00:58 +0400 |
|---|---|---|
| committer | Cyrill Gorcunov <gorcunov@gmail.com> | 2012-11-29 02:17:48 +0400 |
| commit | 3efd91865c31fefb4f61f72fb25b126b2ed5530b (patch) | |
| tree | d4a8012a25c32fed98c9721614731065a3862209 | |
| parent | 0863bc386b2607d9f689d9ff23094e042b54f9eb (diff) | |
| download | nasm-3efd91865c31fefb4f61f72fb25b126b2ed5530b.tar.gz | |
regs: Introduce KNC (Xeon Phi) registers
This patch introduces ZMM0-31 and K0-7 registers.
N.B.: This is initial approach thus everything might
be changed with time, thus this commit is to get foot
wet with new encodings.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
| -rw-r--r-- | opflags.h | 6 | ||||
| -rw-r--r-- | regs.dat | 6 |
2 files changed, 12 insertions, 0 deletions
@@ -162,6 +162,8 @@ typedef uint64_t opflags_t; #define REG_CLASS_RM_MMX GEN_REG_CLASS(4) #define REG_CLASS_RM_XMM GEN_REG_CLASS(5) #define REG_CLASS_RM_YMM GEN_REG_CLASS(6) +#define REG_CLASS_RM_ZMM GEN_REG_CLASS(7) +#define REG_CLASS_KREG GEN_REG_CLASS(8) #define is_class(class, op) (!((opflags_t)(class) & ~(opflags_t)(op))) @@ -186,6 +188,10 @@ typedef uint64_t opflags_t; #define RM_YMM ( REG_CLASS_RM_YMM | REGMEM) /* YMM (AVX) operand */ #define YMMREG ( REG_CLASS_RM_YMM | REGMEM | REGISTER) /* YMM (AVX) register */ #define YMM0 (GEN_SUBCLASS(1) | REG_CLASS_RM_YMM | REGMEM | REGISTER) /* YMM register zero */ +#define ZMMREG ( REG_CLASS_RM_ZMM | REGMEM | REGISTER) /* ZMM (Phi) register */ +#define ZMM0 (GEN_SUBCLASS(1) | REG_CLASS_RM_ZMM | REGMEM | REGISTER) /* ZMM register zero */ +#define KREG0 ( REG_CLASS_KREG | REGISTER) /* K0 (Phi) register */ +#define KREG ( REG_CLASS_KREG | REGISTER) /* K (Phi) register */ #define REG_CDT ( REG_CLASS_CDT | BITS32 | REGISTER) /* CRn, DRn and TRn */ #define REG_CREG (GEN_SUBCLASS(1) | REG_CLASS_CDT | BITS32 | REGISTER) /* CRn */ #define REG_DREG (GEN_SUBCLASS(2) | REG_CLASS_CDT | BITS32 | REGISTER) /* DRn */ @@ -117,3 +117,9 @@ xmm1-15 XMMREG xmmreg 1 # AVX registers ymm0 YMM0 ymmreg 0 ymm1-15 YMMREG ymmreg 1 + +# KNC (Xeon Phi) registers +zmm0 ZMM0 zmmreg 0 +zmm1-31 ZMMREG zmmreg 1 +k0 KREG0 kreg 0 +k1-7 KREG kreg 1 |