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| author | H. Peter Anvin <hpa@zytor.com> | 2007-11-12 22:05:31 -0800 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2007-11-12 22:05:31 -0800 |
| commit | 4b3390eb4714528d94cf1a2aabb12efcdae828d4 (patch) | |
| tree | f93cea64cd8684fe26b64afb2e4d37e62d506479 /test/lar_lsl.asm | |
| parent | e8cdcdcc37d9a701b47a9fc129c912c3b0f9ba68 (diff) | |
| download | nasm-4b3390eb4714528d94cf1a2aabb12efcdae828d4.tar.gz | |
BR 1828866: fix handling of LAR/LSL
Fix handling of LAR/LSL with various sized operands
Diffstat (limited to 'test/lar_lsl.asm')
| -rw-r--r-- | test/lar_lsl.asm | 122 |
1 files changed, 122 insertions, 0 deletions
diff --git a/test/lar_lsl.asm b/test/lar_lsl.asm new file mode 100644 index 00000000..69c56fc9 --- /dev/null +++ b/test/lar_lsl.asm @@ -0,0 +1,122 @@ +; LAR/LSL
+;---------
+
+; 1x ; = invalid due to lack of REX
+; 3x ; = invalid due to Mw
+
+%macro m 1
+
+ bits 16
+
+ %1 ax, ax
+ %1 ax,eax
+; %1 ax,rax
+
+ %1 eax, ax
+ %1 eax,eax
+; %1 eax,rax
+
+; %1 rax, ax
+; %1 rax,eax
+; %1 rax,rax
+
+ %1 ax, [0]
+ %1 ax, word [0]
+;;; %1 ax,dword [0]
+; %1 ax,qword [0]
+
+ %1 eax, [0]
+ %1 eax, word [0]
+;;; %1 eax,dword [0]
+; %1 eax,qword [0]
+
+; %1 rax, [0]
+; %1 rax, word [0]
+; %1 rax,dword [0]
+; %1 rax,qword [0]
+
+ bits 32
+
+ %1 ax, ax
+ %1 ax,eax
+; %1 ax,rax
+
+ %1 eax, ax
+ %1 eax,eax
+; %1 eax,rax
+
+; %1 rax, ax
+; %1 rax,eax
+; %1 rax,rax
+
+ %1 ax, [0]
+ %1 ax, word [0]
+;;; %1 ax,dword [0]
+; %1 ax,qword [0]
+
+ %1 eax, [0]
+ %1 eax, word [0]
+;;; %1 eax,dword [0]
+; %1 eax,qword [0]
+
+; %1 rax, [0]
+; %1 rax, word [0]
+; %1 rax,dword [0]
+; %1 rax,qword [0]
+
+ bits 64
+
+ %1 ax, ax
+ %1 ax,eax
+ %1 ax,rax ; $TODO: shouldn't emit REX.W $
+
+ %1 eax, ax
+ %1 eax,eax
+ %1 eax,rax ; $TODO: shouldn't emit REX.W $
+
+ %1 rax, ax
+ %1 rax,eax
+ %1 rax,rax
+
+ %1 ax, [0]
+ %1 ax, word [0]
+;;; %1 ax,dword [0]
+;;; %1 ax,qword [0]
+
+ %1 eax, [0]
+ %1 eax, word [0]
+;;; %1 eax,dword [0]
+;;; %1 eax,qword [0]
+
+ %1 rax, [0]
+ %1 rax, word [0]
+;;; %1 rax,dword [0]
+;;; %1 rax,qword [0]
+
+%endmacro
+
+m lar
+
+m lsl
+
+bits 16
+lar ax,[ si]
+lar ax,[esi]
+bits 32
+lar ax,[ si]
+lar ax,[esi]
+bits 64
+lar ax,[esi]
+lar ax,[rsi]
+
+bits 16
+lsl ax,[ si]
+lsl ax,[esi]
+bits 32
+lsl ax,[ si]
+lsl ax,[esi]
+bits 64
+lar ax,[esi]
+lsl ax,[rsi]
+
+; EOF
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