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* Merge branch 'ppc-r64-44' into 'master'Niels Möller2022-08-062-0/+277
|\ | | | | | | | | [PowerPC] Implement Poly1305 single block update based on radix 2^64 See merge request nettle/nettle!47
| * [PowerPC] Use defined structure constants of P1305 in asm.m4Maamoun TK2022-08-061-20/+20
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| * [PowerPC] Implement Poly1305 single block update based on radix 2^64Maamoun TK2022-05-292-0/+277
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* | Fix a POSIX violation of m4 argument expansionMaamoun TK2022-06-131-53/+60
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* Fix comment typo.Niels Möller2022-03-171-1/+1
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* ppc: Update fat setup for new ghash organization.Niels Möller2022-02-222-5/+40
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* ppc: Update vpmsumd ghash to new organization.Niels Möller2022-02-223-499/+519
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* ecc: Add powerpc64 assembly for ecc_448_modpMartin Schwenke2022-01-241-0/+174
| | | | | Signed-off-by: Martin Schwenke <martin@meltin.net> Signed-off-by: Amitay Isaacs <amitay@gmail.com>
* Move a comment.Niels Möller2022-01-241-2/+2
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* ecc: Add powerpc64 assembly for ecc_25519_modpMartin Schwenke2022-01-241-0/+101
| | | | | Signed-off-by: Martin Schwenke <martin@meltin.net> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
* ecc: Add powerpc64 assembly for ecc_224_modpAmitay Isaacs2022-01-241-0/+123
| | | | Signed-off-by: Amitay Isaacs <amitay@ozlabs.org>
* ecc: Add powerpc64 assembly for ecc_521_modpMartin Schwenke2022-01-211-0/+166
| | | | | Signed-off-by: Martin Schwenke <martin@meltin.net> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
* ecc: Add powerpc64 assembly for ecc_384_modpMartin Schwenke2022-01-211-0/+227
| | | | | | Signed-off-by: Martin Schwenke <martin@meltin.net> Signed-off-by: Amitay Isaacs <amitay@ozlabs.org> Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
* ecc: Add powerpc64 assembly for ecc_192_modpAmitay Isaacs2022-01-211-0/+87
| | | | Signed-off-by: Amitay Isaacs <amitay@ozlabs.org>
* ppc: Reduce number of registers used for ecc_secp256r1_redc.Niels Möller2022-01-101-42/+26
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* ppc: New configure test for ELFV2_ABINiels Möller2022-01-041-2/+2
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* ppc: Add powerpc64 assembly for ecc_256_redcAmitay Isaacs2021-12-091-0/+144
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* ppc: Fix macro name SWAP_MASK to use all uppercase.Niels Möller2021-04-132-88/+88
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* [PowerPC64] Use 32-bit offset to load datamamonet2020-12-183-6/+10
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* ppc: More interleaving of chacha_4core.Niels Möller2020-12-121-16/+16
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* Merge branch 'ppc-chacha-4core'Niels Möller2020-12-082-0/+314
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| * ppc: Save registers below stack pointer, without modifying it.ppc-chacha-4coreNiels Möller2020-12-011-10/+11
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| * ppc: Optimize chacha_4core main loopNiels Möller2020-12-011-9/+42
| | | | | | | | | | * powerpc64/p7/chacha-4core.asm (QR): Instruction level interleaving in the main loop, written by Torbjörn Granlund.
| * ppc: Workaround using m4_unquote.Niels Möller2020-11-301-1/+1
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| * ppc: Add byte-swapping to chacha_4core, for big-endian builds.Niels Möller2020-11-301-0/+13
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| * ppc: New assembly for chacha_core4, doing four blocks in parallel.Niels Möller2020-11-302-0/+267
| | | | | | | | | | | | | | | | | | | | | | | | | | * chacha-crypt.c: (_nettle_chacha_crypt_4core) (_nettle_chacha_crypt32_4core): New functions. * chacha-internal.h: Add prototypes for _nettle_chacha_4core and related functions. * configure.ac (asm_nettle_optional_list): Add chacha-4core.asm. * powerpc64/fat/chacha-4core.asm: New file. * powerpc64/p7/chacha-4core.asm: New file. * fat-ppc.c (fat_init): When altivec is available, use _nettle_chacha_crypt_4core and _nettle_chacha_crypt32_4core instead of _2core variants.
* | Fix comment typeNiels Möller2020-12-011-1/+1
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* Merge branch 'ppc-gcm' into master-updatesNiels Möller2020-11-282-0/+538
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| * ppc: Enable gcm code in fat builds. Based on patch by Mamone Tarsha.Niels Möller2020-11-261-0/+39
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| * [PowerPC64] modify register defines in gcm-hash.asmmamonet2020-11-251-20/+20
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| * ppc: Fix table offsets in gcm_hash.Maamoun TK2020-11-141-37/+34
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| * ppc: Assembly implementation of gcm_hash.Maamoun TK2020-11-121-0/+502
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* | ppc: Use vaddcuw instruction.Niels Möller2020-11-281-3/+1
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* | ppc: Support big-endian for _chacha_2core.ppc-chacha-2coreNiels Möller2020-11-251-0/+17
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* | ppc: Enable _chacha_2core in fat builds.Niels Möller2020-11-241-0/+36
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* | ppc: Implement _chacha_2core.Niels Möller2020-11-231-0/+249
|/ | | | * powerpc64/p7/chacha-2core.asm: New file.
* ppc: Comment instructions for chacha byte swapping.ppc-chacha-coreNiels Möller2020-11-071-3/+3
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* ppc: Add altivec detection to fat buildsNiels Möller2020-11-071-0/+37
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* ppc: chacha-core big-endian supportMaamoun TK2020-09-281-2/+22
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* ppc: Assembly implementation of _chacha_core.Niels Möller2020-09-251-0/+140
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* "PowerPC64" Use same register convention in VSR macroMaamoun TK2020-09-231-4/+3
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* "PowerPC64" Use explicit register namesMaamoun TK2020-09-233-197/+200
| | | | | This patch is built upon ppc-m4-macrology.patch. Using explicit register names is working as expected now.
* ppc: Add configure test and macros to replace register names.Niels Möller2020-09-211-0/+14
| | | | | | | | | | | | | * aclocal.m4 (GMP_ASM_POWERPC_R_REGISTERS): New configure test, adapted from corresponding test in GMP's acinlude.m4. * configure.ac (ASM_PPC_WANT_R_REGISTERS): New substituted variable. Set using GMP_ASM_POWERPC_R_REGISTERS, when powerpc64 assembly code is enabled. * config.m4.in: Substituted here. * powerpc64/machine.m4: Check ASM_PPC_WANT_R_REGISTERS, and if needed, replace register names like r0, r1, ... with integers. * Makefile.in (%.asm): Include m4-utils.m4 for preprocessing of .asm files, and include config.m4 before machine.m4.
* Use default m4 quote character in asm files, part 5default-m4-quote-charNiels Möller2020-09-145-98/+98
| | | | Update powerpc64 files.
* "PowerPC64" AES improve syntaxMaamoun TK2020-09-044-110/+90
| | | | | | | | | | This patch adds "VSR" macro to improve the syntax of assembly code, I will create a separate patch for gcm-hash since it hasn't merged yet to the master. I also removed the TODO from README because I tried to use "lxv/stxv" in POWER9 instead of "lxvd2x/stxvd2x" but gcc produced "lxvd2x/stxvd2x" in the binary. I'm not sure if it's variant issue of gcc but this will be problematic since "lxvd2x/stxvd2x" need permuting in little-endian mode while "lxv/stxv" is endianness aware.
* Add support for powerpc64 fat buildNiels Möller2020-08-262-0/+74
| | | | Based on patch by Mamone Tarsha
* Rename powerpc64/P8 to powerpc64/p8Niels Möller2020-08-262-0/+0
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* "PowerPC64" Add README (Reformatted)Maamoun TK2020-08-261-0/+73
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* "PowerPC64" Add optimized AES [Enc|Dec]Maamoun TK2020-08-262-0/+711
| | | | | | | | | | | | | I measured the latency and throughput of vcipher/vncipher/vxor instructions for POWER8 vcipher/vncipher throughput 6 instructions per cycle latency 0.91 clock cycles vxor throughput 6 instructions per cycle latency 0.32 clock cycles So the ideal option for POWER8 is processing 8 blocks, it has +12% performance over processing 4 blocks.
* "PowerPC64" Add machine.m4Maamoun TK2020-08-261-0/+32