diff options
Diffstat (limited to 'deps/v8/src/mips64/assembler-mips64.h')
| -rw-r--r-- | deps/v8/src/mips64/assembler-mips64.h | 100 |
1 files changed, 77 insertions, 23 deletions
diff --git a/deps/v8/src/mips64/assembler-mips64.h b/deps/v8/src/mips64/assembler-mips64.h index 7f026bf57c..314970238b 100644 --- a/deps/v8/src/mips64/assembler-mips64.h +++ b/deps/v8/src/mips64/assembler-mips64.h @@ -404,8 +404,8 @@ class MemOperand : public Operand { offset_zero = 0 }; - explicit MemOperand(Register rn, int64_t offset = 0); - explicit MemOperand(Register rn, int64_t unit, int64_t multiplier, + explicit MemOperand(Register rn, int32_t offset = 0); + explicit MemOperand(Register rn, int32_t unit, int32_t multiplier, OffsetAddend offset_addend = offset_zero); int32_t offset() const { return offset_; } @@ -493,19 +493,16 @@ class Assembler : public AssemblerBase { ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); // On MIPS there is no Constant Pool so we skip that parameter. - INLINE(static Address target_address_at(Address pc, - ConstantPoolArray* constant_pool)) { + INLINE(static Address target_address_at(Address pc, Address constant_pool)) { return target_address_at(pc); } - INLINE(static void set_target_address_at(Address pc, - ConstantPoolArray* constant_pool, - Address target, - ICacheFlushMode icache_flush_mode = - FLUSH_ICACHE_IF_NEEDED)) { + INLINE(static void set_target_address_at( + Address pc, Address constant_pool, Address target, + ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED)) { set_target_address_at(pc, target, icache_flush_mode); } INLINE(static Address target_address_at(Address pc, Code* code)) { - ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; + Address constant_pool = code ? code->constant_pool() : NULL; return target_address_at(pc, constant_pool); } INLINE(static void set_target_address_at(Address pc, @@ -513,7 +510,7 @@ class Assembler : public AssemblerBase { Address target, ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED)) { - ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL; + Address constant_pool = code ? code->constant_pool() : NULL; set_target_address_at(pc, constant_pool, target, icache_flush_mode); } @@ -524,6 +521,8 @@ class Assembler : public AssemblerBase { // Return the code target address of the patch debug break slot inline static Address break_address_from_return_address(Address pc); + static void JumpLabelToJumpRegister(Address pc); + static void QuietNaN(HeapObject* nan); // This sets the branch destination (which gets loaded at the call address). @@ -598,6 +597,9 @@ class Assembler : public AssemblerBase { // possible to align the pc offset to a multiple // of m. m must be a power of 2 (>= 4). void Align(int m); + // Insert the smallest number of zero bytes possible to align the pc offset + // to a mulitple of m. m must be a power of 2 (>= 2). + void DataAlign(int m); // Aligns code to something that's optimal for a jump target for the platform. void CodeTargetAlign(); @@ -634,6 +636,10 @@ class Assembler : public AssemblerBase { void b(Label* L) { b(branch_offset(L, false)>>2); } void bal(int16_t offset); void bal(Label* L) { bal(branch_offset(L, false)>>2); } + void bc(int32_t offset); + void bc(Label* L) { bc(branch_offset(L, false) >> 2); } + void balc(int32_t offset); + void balc(Label* L) { balc(branch_offset(L, false) >> 2); } void beq(Register rs, Register rt, int16_t offset); void beq(Register rs, Register rt, Label* L) { @@ -743,8 +749,8 @@ class Assembler : public AssemblerBase { void jal(int64_t target); void jalr(Register rs, Register rd = ra); void jr(Register target); - void j_or_jr(int64_t target, Register rs); - void jal_or_jalr(int64_t target, Register rs); + void jic(Register rt, int16_t offset); + void jialc(Register rt, int16_t offset); // -------Data-processing-instructions--------- @@ -847,6 +853,16 @@ class Assembler : public AssemblerBase { void sd(Register rd, const MemOperand& rs); + // ---------PC-Relative-instructions----------- + + void addiupc(Register rs, int32_t imm19); + void lwpc(Register rs, int32_t offset19); + void lwupc(Register rs, int32_t offset19); + void ldpc(Register rs, int32_t offset18); + void auipc(Register rs, int16_t imm16); + void aluipc(Register rs, int16_t imm16); + + // ----------------Prefetch-------------------- void pref(int32_t hint, const MemOperand& rs); @@ -881,17 +897,36 @@ class Assembler : public AssemblerBase { void movf(Register rd, Register rs, uint16_t cc = 0); void sel(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); + void sel_s(FPURegister fd, FPURegister fs, FPURegister ft); + void sel_d(FPURegister fd, FPURegister fs, FPURegister ft); void seleqz(Register rd, Register rs, Register rt); void seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); void selnez(Register rs, Register rt, Register rd); void selnez(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); + void seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft); + void seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft); + void selnez_d(FPURegister fd, FPURegister fs, FPURegister ft); + void selnez_s(FPURegister fd, FPURegister fs, FPURegister ft); + + void movz_s(FPURegister fd, FPURegister fs, Register rt); + void movz_d(FPURegister fd, FPURegister fs, Register rt); + void movt_s(FPURegister fd, FPURegister fs, uint16_t cc); + void movt_d(FPURegister fd, FPURegister fs, uint16_t cc); + void movf_s(FPURegister fd, FPURegister fs, uint16_t cc); + void movf_d(FPURegister fd, FPURegister fs, uint16_t cc); + void movn_s(FPURegister fd, FPURegister fs, Register rt); + void movn_d(FPURegister fd, FPURegister fs, Register rt); // Bit twiddling. void clz(Register rd, Register rs); void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); void dext_(Register rt, Register rs, uint16_t pos, uint16_t size); + void bitswap(Register rd, Register rt); + void dbitswap(Register rd, Register rt); + void align(Register rd, Register rs, Register rt, uint8_t bp); + void dalign(Register rd, Register rs, Register rt, uint8_t bp); // --------Coprocessor-instructions---------------- @@ -926,10 +961,15 @@ class Assembler : public AssemblerBase { void abs_s(FPURegister fd, FPURegister fs); void abs_d(FPURegister fd, FPURegister fs); void mov_d(FPURegister fd, FPURegister fs); + void mov_s(FPURegister fd, FPURegister fs); void neg_s(FPURegister fd, FPURegister fs); void neg_d(FPURegister fd, FPURegister fs); void sqrt_s(FPURegister fd, FPURegister fs); void sqrt_d(FPURegister fd, FPURegister fs); + void rsqrt_s(FPURegister fd, FPURegister fs); + void rsqrt_d(FPURegister fd, FPURegister fs); + void recip_d(FPURegister fd, FPURegister fs); + void recip_s(FPURegister fd, FPURegister fs); // Conversion. void cvt_w_s(FPURegister fd, FPURegister fs); @@ -958,6 +998,9 @@ class Assembler : public AssemblerBase { void ceil_l_s(FPURegister fd, FPURegister fs); void ceil_l_d(FPURegister fd, FPURegister fs); + void class_s(FPURegister fd, FPURegister fs); + void class_d(FPURegister fd, FPURegister fs); + void min(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); void mina(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); void max(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); @@ -982,6 +1025,8 @@ class Assembler : public AssemblerBase { // Conditions and branches for MIPSr6. void cmp(FPUCondition cond, SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs); + void cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); + void cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); void bc1eqz(int16_t offset, FPURegister ft); void bc1eqz(Label* L, FPURegister ft) { @@ -995,6 +1040,8 @@ class Assembler : public AssemblerBase { // Conditions and branches for non MIPSr6. void c(FPUCondition cond, SecondaryField fmt, FPURegister ft, FPURegister fs, uint16_t cc = 0); + void c_s(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); + void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); void bc1f(int16_t offset, uint16_t cc = 0); void bc1f(Label* L, uint16_t cc = 0) { @@ -1088,6 +1135,8 @@ class Assembler : public AssemblerBase { // inline tables, e.g., jump-tables. void db(uint8_t data); void dd(uint32_t data); + void dq(uint64_t data); + void dp(uintptr_t data) { dq(data); } void dd(Label* label); // Emits the address of the code stub's first instruction. @@ -1105,7 +1154,9 @@ class Assembler : public AssemblerBase { inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; } // Get the number of bytes available in the buffer. - inline int available_space() const { return reloc_info_writer.pos() - pc_; } + inline intptr_t available_space() const { + return reloc_info_writer.pos() - pc_; + } // Read/patch instructions. static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); } @@ -1172,11 +1223,12 @@ class Assembler : public AssemblerBase { void CheckTrampolinePool(); - // Allocate a constant pool of the correct size for the generated code. - Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate); - - // Generate the constant pool for the generated code. - void PopulateConstantPool(ConstantPoolArray* constant_pool); + void PatchConstantPoolAccessInstruction(int pc_offset, int offset, + ConstantPoolEntry::Access access, + ConstantPoolEntry::Type type) { + // No embedded constant pool support. + UNREACHABLE(); + } protected: // Relocation for a type-recording IC has the AST id added to it. This @@ -1352,6 +1404,8 @@ class Assembler : public AssemblerBase { Register r1, FPURegister r2, int32_t j); + void GenInstrImmediate(Opcode opcode, Register rs, int32_t j); + void GenInstrImmediate(Opcode opcode, int32_t offset26); void GenInstrJump(Opcode opcode, @@ -1418,13 +1472,13 @@ class Assembler : public AssemblerBase { int32_t get_trampoline_entry(int32_t pos); int unbound_labels_count_; - // If trampoline is emitted, generated code is becoming large. As this is - // already a slow case which can possibly break our code generation for the - // extreme case, we use this information to trigger different mode of + // After trampoline is emitted, long branches are used in generated code for + // the forward branches whose target offsets could be beyond reach of branch + // instruction. We use this information to trigger different mode of // branch instruction generation, where we use jump instructions rather // than regular branch instructions. bool trampoline_emitted_; - static const int kTrampolineSlotsSize = 6 * kInstrSize; + static const int kTrampolineSlotsSize = 2 * kInstrSize; static const int kMaxBranchOffset = (1 << (18 - 1)) - 1; static const int kInvalidSlotPos = -1; |