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authorAlexandre Courbot <acourbot@nvidia.com>2015-06-08 12:47:18 +0900
committerAlexandre Courbot <acourbot@nvidia.com>2015-08-06 13:26:23 +0900
commitd612685ed1e6fa9fd10c70f312ddcc655c19a992 (patch)
tree3367f1354652913fee568745ae44843054fcdea8
parentcb2d45df70cce638f00fb36264e974acee4cf943 (diff)
downloadnouveau-d612685ed1e6fa9fd10c70f312ddcc655c19a992.tar.gz
HACK fix gk20a
-rw-r--r--drm/nouveau/nouveau_display.c3
-rw-r--r--drm/nouveau/nouveau_drm.c2
-rw-r--r--drm/nouveau/nvkm/subdev/clk/gm20b.c2
3 files changed, 5 insertions, 2 deletions
diff --git a/drm/nouveau/nouveau_display.c b/drm/nouveau/nouveau_display.c
index 828c8775a..70bbfb77f 100644
--- a/drm/nouveau/nouveau_display.c
+++ b/drm/nouveau/nouveau_display.c
@@ -154,9 +154,12 @@ nouveau_display_vblstamp(struct drm_device *dev, int head, int *max_error,
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
if (nouveau_crtc(crtc)->index == head) {
+ /*
return drm_calc_vbltimestamp_from_scanoutpos(dev,
head, max_error, time, flags, crtc,
&crtc->hwmode);
+ */
+ return 0;
}
}
diff --git a/drm/nouveau/nouveau_drm.c b/drm/nouveau/nouveau_drm.c
index ebe5eb6d0..bde719539 100644
--- a/drm/nouveau/nouveau_drm.c
+++ b/drm/nouveau/nouveau_drm.c
@@ -965,7 +965,7 @@ driver_stub = {
.get_vblank_counter = drm_vblank_count,
.enable_vblank = nouveau_display_vblank_enable,
.disable_vblank = nouveau_display_vblank_disable,
- .get_scanout_position = nouveau_display_scanoutpos,
+ //.get_scanout_position = nouveau_display_scanoutpos,
.get_vblank_timestamp = nouveau_display_vblstamp,
.ioctls = nouveau_ioctls,
diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c
index 85ea1b8b9..fb0337fcd 100644
--- a/drm/nouveau/nvkm/subdev/clk/gm20b.c
+++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c
@@ -1015,7 +1015,7 @@ gm20b_napll_setup(struct gm20b_clk_priv *priv)
GPCPLL_DVFS1_DFS_CAL_DONE_BIT,
GPCPLL_DVFS1_DFS_CAL_DONE_BIT)) {
nv_error(priv, "%s: DVFS calibration timeout\n", __func__);
- return -ETIMEDOUT;
+ //return -ETIMEDOUT;
}
val = nv_rd32(priv, GPCPLL_CFG3);