diff options
| author | Martin Peres <martin.peres@free.fr> | 2014-08-17 17:33:09 +0200 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-25 08:37:32 +1000 |
| commit | 4fcb7b80988dc351b0081b58b58d888c5693684a (patch) | |
| tree | a42f555fb4c32dafa9d552fd7cf3288d3633898f | |
| parent | 396c25045cfe926c4bc92789b6c76c146fb6978a (diff) | |
| download | nouveau-4fcb7b80988dc351b0081b58b58d888c5693684a.tar.gz | |
ppwr: enable ppwr on gm107
For some reason, it is now required to wait a 20 µs after the 0x200 reset of
the engine.
Signed-off-by: Martin Peres <martin.peres@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | nvkm/engine/device/gm100.c | 3 | ||||
| -rw-r--r-- | nvkm/subdev/pwr/base.c | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/nvkm/engine/device/gm100.c b/nvkm/engine/device/gm100.c index 136dd9840..9e9f5670f 100644 --- a/nvkm/engine/device/gm100.c +++ b/nvkm/engine/device/gm100.c @@ -75,8 +75,9 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; -#if 0 device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; + +#if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; diff --git a/nvkm/subdev/pwr/base.c b/nvkm/subdev/pwr/base.c index 69f1f34f6..477c9a214 100644 --- a/nvkm/subdev/pwr/base.c +++ b/nvkm/subdev/pwr/base.c @@ -204,6 +204,9 @@ _nouveau_pwr_init(struct nouveau_object *object) nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000); nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000); + /* At least one GM107 needs this delay after reset */ + udelay(20); + /* upload data segment */ nv_wr32(ppwr, 0x10a1c0, 0x01000000); for (i = 0; i < impl->data.size / 4; i++) |