diff options
| author | Ken Adams <tinsulpop@gmail.com> | 2015-10-20 14:49:37 -0400 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2015-11-10 16:42:20 +0900 |
| commit | 0d97f256240426be4dfc318d2d35c3ea2d1c659a (patch) | |
| tree | 00ecfb1132a9b1e24c129075823b20c14ed40dc4 | |
| parent | d5fbab716a0e0f74a759b38c44c2ba115dfee700 (diff) | |
| download | nouveau-0d97f256240426be4dfc318d2d35c3ea2d1c659a.tar.gz | |
hwref: hardware reference headers
These headers are generated from NVIDIA-internal hardware
manuals. For this check-in all chips Nouveau supports
>= nv50/g80 are included.
Signed-off-by: Ken Adams <kadams@nvidia.com>
598 files changed, 59004 insertions, 0 deletions
diff --git a/drm/nouveau/include/nvkm/hwref/g200/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/g200/nv_bus_hwref.h new file mode 100644 index 000000000..b0be5dc3d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g200/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g200_bus_hwref_h__ +#define __nv_g200_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_g200_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g200/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/g200/nv_fifo_hwref.h new file mode 100644 index 000000000..ee19d4f51 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g200/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g200_fifo_hwref_h__ +#define __nv_g200_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_g200_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g200/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/g200/nv_flush_hwref.h new file mode 100644 index 000000000..36e3c103f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g200/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g200_flush_hwref_h__ +#define __nv_g200_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_g200_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g200/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/g200/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..63fcebd1c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g200/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g200_graphics_nobundle_hwref_h__ +#define __nv_g200_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_g200_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g200/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/g200/nv_master_hwref.h new file mode 100644 index 000000000..93eb7f1de --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g200/nv_master_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g200_master_hwref_h__ +#define __nv_g200_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_1 0x680 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x540 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_g200_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g200/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/g200/nv_mmu_hwref.h new file mode 100644 index 000000000..ff11409d4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g200/nv_mmu_hwref.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g200_mmu_hwref_h__ +#define __nv_g200_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 +#define NV_MMU_PTE_KIND_Z16 0x68 +#define NV_MMU_PTE_KIND_X8C24 0x44 + +#endif /* __nv_g200_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g200/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/g200/nv_ram_hwref.h new file mode 100644 index 000000000..e723b8703 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g200/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g200_ram_hwref_h__ +#define __nv_g200_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_g200_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g200/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/g200/nv_therm_hwref.h new file mode 100644 index 000000000..6ef816442 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g200/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g200_therm_hwref_h__ +#define __nv_g200_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_g200_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g200/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/g200/nv_timer_hwref.h new file mode 100644 index 000000000..c4ae4d0a4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g200/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g200_timer_hwref_h__ +#define __nv_g200_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_g200_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g80/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/g80/nv_bus_hwref.h new file mode 100644 index 000000000..21a23a9e1 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g80/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g80_bus_hwref_h__ +#define __nv_g80_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_g80_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g80/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/g80/nv_fifo_hwref.h new file mode 100644 index 000000000..bb9bebd2d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g80/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g80_fifo_hwref_h__ +#define __nv_g80_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_g80_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g80/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/g80/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..fe00080c2 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g80/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g80_graphics_nobundle_hwref_h__ +#define __nv_g80_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_g80_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g80/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/g80/nv_master_hwref.h new file mode 100644 index 000000000..03f22fc01 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g80/nv_master_hwref.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g80_master_hwref_h__ +#define __nv_g80_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_g80_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g80/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/g80/nv_mmu_hwref.h new file mode 100644 index 000000000..7c0dd5db3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g80/nv_mmu_hwref.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g80_mmu_hwref_h__ +#define __nv_g80_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 + +#endif /* __nv_g80_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g80/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/g80/nv_ram_hwref.h new file mode 100644 index 000000000..6c1a8d189 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g80/nv_ram_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g80_ram_hwref_h__ +#define __nv_g80_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) + +#endif /* __nv_g80_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g80/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/g80/nv_therm_hwref.h new file mode 100644 index 000000000..5d5617311 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g80/nv_therm_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g80_therm_hwref_h__ +#define __nv_g80_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 + +#endif /* __nv_g80_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g80/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/g80/nv_timer_hwref.h new file mode 100644 index 000000000..d2d4fa53b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g80/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g80_timer_hwref_h__ +#define __nv_g80_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_g80_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g84/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/g84/nv_bus_hwref.h new file mode 100644 index 000000000..86770ed66 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g84/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g84_bus_hwref_h__ +#define __nv_g84_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_g84_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g84/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/g84/nv_fifo_hwref.h new file mode 100644 index 000000000..8a0a97c0b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g84/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g84_fifo_hwref_h__ +#define __nv_g84_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_g84_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g84/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/g84/nv_flush_hwref.h new file mode 100644 index 000000000..81adb3bcf --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g84/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g84_flush_hwref_h__ +#define __nv_g84_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_g84_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g84/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/g84/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..54cdd4227 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g84/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g84_graphics_nobundle_hwref_h__ +#define __nv_g84_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_g84_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g84/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/g84/nv_master_hwref.h new file mode 100644 index 000000000..a913659e6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g84/nv_master_hwref.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g84_master_hwref_h__ +#define __nv_g84_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_g84_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g84/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/g84/nv_mmu_hwref.h new file mode 100644 index 000000000..70b7d4daf --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g84/nv_mmu_hwref.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g84_mmu_hwref_h__ +#define __nv_g84_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 + +#endif /* __nv_g84_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g84/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/g84/nv_ram_hwref.h new file mode 100644 index 000000000..8e2a68461 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g84/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g84_ram_hwref_h__ +#define __nv_g84_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_g84_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g84/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/g84/nv_therm_hwref.h new file mode 100644 index 000000000..ed7677810 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g84/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g84_therm_hwref_h__ +#define __nv_g84_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_g84_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g84/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/g84/nv_timer_hwref.h new file mode 100644 index 000000000..1d3c63ee9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g84/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g84_timer_hwref_h__ +#define __nv_g84_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_g84_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g86/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/g86/nv_bus_hwref.h new file mode 100644 index 000000000..7ccb5e530 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g86/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g86_bus_hwref_h__ +#define __nv_g86_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_g86_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g86/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/g86/nv_fifo_hwref.h new file mode 100644 index 000000000..987fd3cea --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g86/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g86_fifo_hwref_h__ +#define __nv_g86_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_g86_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g86/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/g86/nv_flush_hwref.h new file mode 100644 index 000000000..8c334f8fb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g86/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g86_flush_hwref_h__ +#define __nv_g86_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_g86_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g86/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/g86/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..1c3e46799 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g86/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g86_graphics_nobundle_hwref_h__ +#define __nv_g86_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_g86_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g86/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/g86/nv_master_hwref.h new file mode 100644 index 000000000..ce87cae57 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g86/nv_master_hwref.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g86_master_hwref_h__ +#define __nv_g86_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_g86_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g86/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/g86/nv_mmu_hwref.h new file mode 100644 index 000000000..de50ab553 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g86/nv_mmu_hwref.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g86_mmu_hwref_h__ +#define __nv_g86_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 + +#endif /* __nv_g86_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g86/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/g86/nv_ram_hwref.h new file mode 100644 index 000000000..b34b61507 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g86/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g86_ram_hwref_h__ +#define __nv_g86_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_g86_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g86/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/g86/nv_therm_hwref.h new file mode 100644 index 000000000..1de7ffbb5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g86/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g86_therm_hwref_h__ +#define __nv_g86_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_g86_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g86/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/g86/nv_timer_hwref.h new file mode 100644 index 000000000..4cc7bcb16 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g86/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g86_timer_hwref_h__ +#define __nv_g86_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_g86_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g92/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/g92/nv_bus_hwref.h new file mode 100644 index 000000000..20621cc11 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g92/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g92_bus_hwref_h__ +#define __nv_g92_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_g92_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g92/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/g92/nv_fifo_hwref.h new file mode 100644 index 000000000..1a76b1ecd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g92/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g92_fifo_hwref_h__ +#define __nv_g92_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_g92_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g92/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/g92/nv_flush_hwref.h new file mode 100644 index 000000000..a70cd078d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g92/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g92_flush_hwref_h__ +#define __nv_g92_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_g92_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g92/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/g92/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..9eb0f51eb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g92/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g92_graphics_nobundle_hwref_h__ +#define __nv_g92_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_g92_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g92/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/g92/nv_master_hwref.h new file mode 100644 index 000000000..989b11d75 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g92/nv_master_hwref.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g92_master_hwref_h__ +#define __nv_g92_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_g92_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g92/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/g92/nv_mmu_hwref.h new file mode 100644 index 000000000..a17c2f777 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g92/nv_mmu_hwref.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g92_mmu_hwref_h__ +#define __nv_g92_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 + +#endif /* __nv_g92_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g92/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/g92/nv_ram_hwref.h new file mode 100644 index 000000000..31c2c7fc6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g92/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g92_ram_hwref_h__ +#define __nv_g92_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_g92_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g92/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/g92/nv_therm_hwref.h new file mode 100644 index 000000000..a3f9be365 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g92/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g92_therm_hwref_h__ +#define __nv_g92_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_g92_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g92/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/g92/nv_timer_hwref.h new file mode 100644 index 000000000..5a58681be --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g92/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g92_timer_hwref_h__ +#define __nv_g92_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_g92_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g94/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/g94/nv_bus_hwref.h new file mode 100644 index 000000000..b2334610e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g94/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g94_bus_hwref_h__ +#define __nv_g94_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_g94_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g94/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/g94/nv_fifo_hwref.h new file mode 100644 index 000000000..70b040e00 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g94/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g94_fifo_hwref_h__ +#define __nv_g94_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_g94_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g94/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/g94/nv_flush_hwref.h new file mode 100644 index 000000000..b2b00f045 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g94/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g94_flush_hwref_h__ +#define __nv_g94_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_g94_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g94/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/g94/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..5041c4b26 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g94/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g94_graphics_nobundle_hwref_h__ +#define __nv_g94_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_g94_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g94/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/g94/nv_master_hwref.h new file mode 100644 index 000000000..9c9661955 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g94/nv_master_hwref.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g94_master_hwref_h__ +#define __nv_g94_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_g94_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g94/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/g94/nv_mmu_hwref.h new file mode 100644 index 000000000..19fc71d22 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g94/nv_mmu_hwref.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g94_mmu_hwref_h__ +#define __nv_g94_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 + +#endif /* __nv_g94_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g94/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/g94/nv_ram_hwref.h new file mode 100644 index 000000000..3fe2d86fb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g94/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g94_ram_hwref_h__ +#define __nv_g94_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_g94_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g94/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/g94/nv_therm_hwref.h new file mode 100644 index 000000000..138f0a022 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g94/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g94_therm_hwref_h__ +#define __nv_g94_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_g94_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g94/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/g94/nv_timer_hwref.h new file mode 100644 index 000000000..0c668150e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g94/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g94_timer_hwref_h__ +#define __nv_g94_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_g94_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g96/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/g96/nv_bus_hwref.h new file mode 100644 index 000000000..e5d1b125a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g96/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g96_bus_hwref_h__ +#define __nv_g96_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_g96_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g96/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/g96/nv_fifo_hwref.h new file mode 100644 index 000000000..6a1c310d6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g96/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g96_fifo_hwref_h__ +#define __nv_g96_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_g96_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g96/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/g96/nv_flush_hwref.h new file mode 100644 index 000000000..aa065112e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g96/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g96_flush_hwref_h__ +#define __nv_g96_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_g96_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g96/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/g96/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..9b1618054 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g96/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g96_graphics_nobundle_hwref_h__ +#define __nv_g96_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_g96_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g96/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/g96/nv_master_hwref.h new file mode 100644 index 000000000..edc686adf --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g96/nv_master_hwref.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g96_master_hwref_h__ +#define __nv_g96_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_g96_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g96/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/g96/nv_mmu_hwref.h new file mode 100644 index 000000000..1c7c667f6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g96/nv_mmu_hwref.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g96_mmu_hwref_h__ +#define __nv_g96_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 + +#endif /* __nv_g96_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g96/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/g96/nv_ram_hwref.h new file mode 100644 index 000000000..4d4c5b28e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g96/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g96_ram_hwref_h__ +#define __nv_g96_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_g96_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g96/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/g96/nv_therm_hwref.h new file mode 100644 index 000000000..eb9c32774 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g96/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g96_therm_hwref_h__ +#define __nv_g96_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_g96_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g96/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/g96/nv_timer_hwref.h new file mode 100644 index 000000000..24bb531e7 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g96/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g96_timer_hwref_h__ +#define __nv_g96_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_g96_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g98/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/g98/nv_bus_hwref.h new file mode 100644 index 000000000..9b9a58746 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g98/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g98_bus_hwref_h__ +#define __nv_g98_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_g98_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g98/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/g98/nv_fifo_hwref.h new file mode 100644 index 000000000..7399251b0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g98/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g98_fifo_hwref_h__ +#define __nv_g98_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_g98_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g98/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/g98/nv_flush_hwref.h new file mode 100644 index 000000000..7136ce690 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g98/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g98_flush_hwref_h__ +#define __nv_g98_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_g98_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g98/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/g98/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..f568e1b16 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g98/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g98_graphics_nobundle_hwref_h__ +#define __nv_g98_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_g98_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g98/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/g98/nv_master_hwref.h new file mode 100644 index 000000000..df0d416c7 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g98/nv_master_hwref.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g98_master_hwref_h__ +#define __nv_g98_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_g98_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g98/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/g98/nv_mmu_hwref.h new file mode 100644 index 000000000..44f955f19 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g98/nv_mmu_hwref.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g98_mmu_hwref_h__ +#define __nv_g98_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 + +#endif /* __nv_g98_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g98/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/g98/nv_ram_hwref.h new file mode 100644 index 000000000..7ce643635 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g98/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g98_ram_hwref_h__ +#define __nv_g98_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_g98_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g98/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/g98/nv_therm_hwref.h new file mode 100644 index 000000000..f309c539e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g98/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g98_therm_hwref_h__ +#define __nv_g98_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_g98_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/g98/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/g98/nv_timer_hwref.h new file mode 100644 index 000000000..9830f0da1 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/g98/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_g98_timer_hwref_h__ +#define __nv_g98_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_g98_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_bus_hwref.h new file mode 100644 index 000000000..094004e46 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_bus_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_bus_hwref_h__ +#define __nv_gf100_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 + +#endif /* __nv_gf100_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..f78ddc68f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_ctxsw_prog_addendum_hwref_h__ +#define __nv_gf100_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gf100_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..352d844d0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_ctxsw_prog_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_ctxsw_prog_hwref_h__ +#define __nv_gf100_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab + +#endif /* __nv_gf100_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_fb_hwref.h new file mode 100644 index 000000000..0bad8ea90 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_fb_hwref_h__ +#define __nv_gf100_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gf100_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_fifo_hwref.h new file mode 100644 index 000000000..eeffbd5c3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_fifo_hwref.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_fifo_hwref_h__ +#define __nv_gf100_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 11:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*4) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 18:17 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 24:24 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 28:28 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_PBDMA_STATUS 0x26c0 + +#endif /* __nv_gf100_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_flush_hwref.h new file mode 100644 index 000000000..01607775a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_flush_hwref_h__ +#define __nv_gf100_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gf100_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..e6eeeeec8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_graphics_nobundle_hwref.h @@ -0,0 +1,721 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_graphics_nobundle_hwref_h__ +#define __nv_gf100_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 + +#endif /* __nv_gf100_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_ltc_hwref.h new file mode 100644 index 000000000..290e32bfb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_ltc_hwref.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_ltc_hwref_h__ +#define __nv_gf100_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gf100_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_master_hwref.h new file mode 100644 index 000000000..1143a3195 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_master_hwref.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_master_hwref_h__ +#define __nv_gf100_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) + +#endif /* __nv_gf100_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_mmu_hwref.h new file mode 100644 index 000000000..c96dbf327 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_mmu_hwref.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_mmu_hwref_h__ +#define __nv_gf100_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd + +#endif /* __nv_gf100_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_pbdma_hwref.h new file mode 100644 index 000000000..f3b91be15 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_pbdma_hwref.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_pbdma_hwref_h__ +#define __nv_gf100_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:12 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gf100_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..dd4c965cb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_pri_ringmaster_hwref_h__ +#define __nv_gf100_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x121c60 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x121c58 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x121c5c +#define NV_PPRIV_MASTER_RING_COMMAND 0x121c4c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x121c48 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x121c50 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x121c74 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x121c78 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gf100_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..d97c70755 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_pri_ringstation_sys_hwref_h__ +#define __nv_gf100_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gf100_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_proj_hwref.h new file mode 100644 index 000000000..f02b4f32e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_proj_hwref.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_proj_hwref_h__ +#define __nv_gf100_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 4 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 4 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gf100_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..c58fc1a46 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_pwr_pri_hwref.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_pwr_pri_hwref_h__ +#define __nv_gf100_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gf100_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_ram_hwref.h new file mode 100644 index 000000000..a0c8d53dc --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_ram_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_ram_hwref_h__ +#define __nv_gf100_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 12 +#define NV_RAMRL_ENTRY_CHID (0*32+6):(0*32+0) + +#endif /* __nv_gf100_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_therm_hwref.h new file mode 100644 index 000000000..d88ca8f12 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_therm_hwref_h__ +#define __nv_gf100_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gf100_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_timer_hwref.h new file mode 100644 index 000000000..760809803 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_timer_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_timer_hwref_h__ +#define __nv_gf100_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gf100_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_top_hwref.h new file mode 100644 index 000000000..40694699f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_top_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_top_hwref_h__ +#define __nv_gf100_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 + +#endif /* __nv_gf100_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf100/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gf100/nv_trim_hwref.h new file mode 100644 index 000000000..41e977aac --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf100/nv_trim_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf100_trim_hwref_h__ +#define __nv_gf100_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gf100_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_bus_hwref.h new file mode 100644 index 000000000..810b6cbb1 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_bus_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_bus_hwref_h__ +#define __nv_gf104_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 + +#endif /* __nv_gf104_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..13e18205a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_ctxsw_prog_addendum_hwref_h__ +#define __nv_gf104_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gf104_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..fc5b9f923 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_ctxsw_prog_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_ctxsw_prog_hwref_h__ +#define __nv_gf104_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab + +#endif /* __nv_gf104_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_fb_hwref.h new file mode 100644 index 000000000..dab1447a4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_fb_hwref_h__ +#define __nv_gf104_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gf104_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_fifo_hwref.h new file mode 100644 index 000000000..c0d3dfbc2 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_fifo_hwref.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_fifo_hwref_h__ +#define __nv_gf104_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 11:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*4) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 18:17 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 24:24 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 28:28 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_PBDMA_STATUS 0x26c0 + +#endif /* __nv_gf104_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_flush_hwref.h new file mode 100644 index 000000000..a34d92969 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_flush_hwref_h__ +#define __nv_gf104_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gf104_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..2bf508abd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_graphics_nobundle_hwref.h @@ -0,0 +1,725 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_graphics_nobundle_hwref_h__ +#define __nv_gf104_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 + +#endif /* __nv_gf104_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_ltc_hwref.h new file mode 100644 index 000000000..39d414399 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_ltc_hwref.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_ltc_hwref_h__ +#define __nv_gf104_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gf104_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_master_hwref.h new file mode 100644 index 000000000..7f47904be --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_master_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_master_hwref_h__ +#define __nv_gf104_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c + +#endif /* __nv_gf104_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_mmu_hwref.h new file mode 100644 index 000000000..c48208438 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_mmu_hwref.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_mmu_hwref_h__ +#define __nv_gf104_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd + +#endif /* __nv_gf104_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_pbdma_hwref.h new file mode 100644 index 000000000..cd76153d9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_pbdma_hwref.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_pbdma_hwref_h__ +#define __nv_gf104_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:12 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gf104_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..537cbdedf --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_pri_ringmaster_hwref_h__ +#define __nv_gf104_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x121c60 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x121c58 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x121c5c +#define NV_PPRIV_MASTER_RING_COMMAND 0x121c4c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x121c48 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x121c50 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x121c74 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x121c78 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gf104_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..27b24c550 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_pri_ringstation_sys_hwref_h__ +#define __nv_gf104_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gf104_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_proj_hwref.h new file mode 100644 index 000000000..f55d3e8ed --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_proj_hwref.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_proj_hwref_h__ +#define __nv_gf104_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 4 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 4 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gf104_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..e46a78018 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_pwr_pri_hwref.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_pwr_pri_hwref_h__ +#define __nv_gf104_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gf104_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_ram_hwref.h new file mode 100644 index 000000000..84f828341 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_ram_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_ram_hwref_h__ +#define __nv_gf104_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 12 +#define NV_RAMRL_ENTRY_CHID (0*32+6):(0*32+0) + +#endif /* __nv_gf104_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_therm_hwref.h new file mode 100644 index 000000000..d87aee85c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_therm_hwref_h__ +#define __nv_gf104_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gf104_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_timer_hwref.h new file mode 100644 index 000000000..388e203d6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_timer_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_timer_hwref_h__ +#define __nv_gf104_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gf104_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_top_hwref.h new file mode 100644 index 000000000..187ffb7fb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_top_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_top_hwref_h__ +#define __nv_gf104_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 + +#endif /* __nv_gf104_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf104/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gf104/nv_trim_hwref.h new file mode 100644 index 000000000..8ea1a7ca9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf104/nv_trim_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf104_trim_hwref_h__ +#define __nv_gf104_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gf104_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_bus_hwref.h new file mode 100644 index 000000000..e8ffd057e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_bus_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_bus_hwref_h__ +#define __nv_gf106_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 + +#endif /* __nv_gf106_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..550592fc8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_ctxsw_prog_addendum_hwref_h__ +#define __nv_gf106_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gf106_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..64ac72797 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_ctxsw_prog_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_ctxsw_prog_hwref_h__ +#define __nv_gf106_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab + +#endif /* __nv_gf106_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_fb_hwref.h new file mode 100644 index 000000000..7d2058940 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_fb_hwref_h__ +#define __nv_gf106_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gf106_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_fifo_hwref.h new file mode 100644 index 000000000..e0a949864 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_fifo_hwref.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_fifo_hwref_h__ +#define __nv_gf106_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 11:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*4) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 18:17 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 24:24 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 28:28 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_PBDMA_STATUS 0x26c0 + +#endif /* __nv_gf106_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_flush_hwref.h new file mode 100644 index 000000000..bb5b9be16 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_flush_hwref_h__ +#define __nv_gf106_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gf106_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..61ea0d8aa --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_graphics_nobundle_hwref.h @@ -0,0 +1,725 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_graphics_nobundle_hwref_h__ +#define __nv_gf106_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 + +#endif /* __nv_gf106_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_ltc_hwref.h new file mode 100644 index 000000000..9ff351941 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_ltc_hwref.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_ltc_hwref_h__ +#define __nv_gf106_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gf106_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_master_hwref.h new file mode 100644 index 000000000..8b2ea0950 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_master_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_master_hwref_h__ +#define __nv_gf106_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c + +#endif /* __nv_gf106_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_mmu_hwref.h new file mode 100644 index 000000000..6cd53766d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_mmu_hwref.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_mmu_hwref_h__ +#define __nv_gf106_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd + +#endif /* __nv_gf106_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_pbdma_hwref.h new file mode 100644 index 000000000..92fdb5253 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_pbdma_hwref.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_pbdma_hwref_h__ +#define __nv_gf106_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:12 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gf106_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..0fc1b83e6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_pri_ringmaster_hwref_h__ +#define __nv_gf106_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x121c60 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x121c58 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x121c5c +#define NV_PPRIV_MASTER_RING_COMMAND 0x121c4c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x121c48 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x121c50 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x121c74 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x121c78 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gf106_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..008150551 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_pri_ringstation_sys_hwref_h__ +#define __nv_gf106_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gf106_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_proj_hwref.h new file mode 100644 index 000000000..25f86e08b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_proj_hwref.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_proj_hwref_h__ +#define __nv_gf106_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 4 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 4 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gf106_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..b622b28d0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_pwr_pri_hwref.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_pwr_pri_hwref_h__ +#define __nv_gf106_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gf106_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_ram_hwref.h new file mode 100644 index 000000000..1a256d0bd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_ram_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_ram_hwref_h__ +#define __nv_gf106_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 12 +#define NV_RAMRL_ENTRY_CHID (0*32+6):(0*32+0) + +#endif /* __nv_gf106_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_therm_hwref.h new file mode 100644 index 000000000..e022905ae --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_therm_hwref_h__ +#define __nv_gf106_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gf106_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_timer_hwref.h new file mode 100644 index 000000000..4544160b3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_timer_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_timer_hwref_h__ +#define __nv_gf106_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gf106_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_top_hwref.h new file mode 100644 index 000000000..46189a9e7 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_top_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_top_hwref_h__ +#define __nv_gf106_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 + +#endif /* __nv_gf106_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf106/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gf106/nv_trim_hwref.h new file mode 100644 index 000000000..d56710985 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf106/nv_trim_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf106_trim_hwref_h__ +#define __nv_gf106_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gf106_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_bus_hwref.h new file mode 100644 index 000000000..c1a620434 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_bus_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_bus_hwref_h__ +#define __nv_gf108_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 + +#endif /* __nv_gf108_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..ecc45e377 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_ctxsw_prog_addendum_hwref_h__ +#define __nv_gf108_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gf108_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..e8271877c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_ctxsw_prog_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_ctxsw_prog_hwref_h__ +#define __nv_gf108_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab + +#endif /* __nv_gf108_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_fb_hwref.h new file mode 100644 index 000000000..e80458aeb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_fb_hwref_h__ +#define __nv_gf108_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gf108_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_fifo_hwref.h new file mode 100644 index 000000000..fdf83a0ea --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_fifo_hwref.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_fifo_hwref_h__ +#define __nv_gf108_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 11:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*4) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 18:17 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 24:24 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 28:28 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_PBDMA_STATUS 0x26c0 + +#endif /* __nv_gf108_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_flush_hwref.h new file mode 100644 index 000000000..82460b800 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_flush_hwref_h__ +#define __nv_gf108_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gf108_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..ecd573dea --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_graphics_nobundle_hwref.h @@ -0,0 +1,744 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_graphics_nobundle_hwref_h__ +#define __nv_gf108_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 + +#endif /* __nv_gf108_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_ltc_hwref.h new file mode 100644 index 000000000..f93b53578 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_ltc_hwref.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_ltc_hwref_h__ +#define __nv_gf108_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gf108_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_master_hwref.h new file mode 100644 index 000000000..badade581 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_master_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_master_hwref_h__ +#define __nv_gf108_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c + +#endif /* __nv_gf108_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_mmu_hwref.h new file mode 100644 index 000000000..667445f3a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_mmu_hwref.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_mmu_hwref_h__ +#define __nv_gf108_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd + +#endif /* __nv_gf108_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_pbdma_hwref.h new file mode 100644 index 000000000..597db9e0f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_pbdma_hwref.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_pbdma_hwref_h__ +#define __nv_gf108_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 1 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:12 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 1 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gf108_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..aa54aafe9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_pri_ringmaster_hwref_h__ +#define __nv_gf108_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x121c60 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x121c58 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x121c5c +#define NV_PPRIV_MASTER_RING_COMMAND 0x121c4c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x121c48 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x121c50 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x121c74 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x121c78 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gf108_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..e83b5c07c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_pri_ringstation_sys_hwref_h__ +#define __nv_gf108_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gf108_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_proj_hwref.h new file mode 100644 index 000000000..cd7c12790 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_proj_hwref.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_proj_hwref_h__ +#define __nv_gf108_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 1 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 1 +#define NV_SCAL_LITTER_NUM_GPCS 1 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gf108_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..0a743a72f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_pwr_pri_hwref.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_pwr_pri_hwref_h__ +#define __nv_gf108_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gf108_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_ram_hwref.h new file mode 100644 index 000000000..2104391af --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_ram_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_ram_hwref_h__ +#define __nv_gf108_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 12 +#define NV_RAMRL_ENTRY_CHID (0*32+6):(0*32+0) + +#endif /* __nv_gf108_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_therm_hwref.h new file mode 100644 index 000000000..6f406952d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_therm_hwref_h__ +#define __nv_gf108_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gf108_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_timer_hwref.h new file mode 100644 index 000000000..cd738c4f4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_timer_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_timer_hwref_h__ +#define __nv_gf108_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gf108_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_top_hwref.h new file mode 100644 index 000000000..c0dc6a4d5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_top_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_top_hwref_h__ +#define __nv_gf108_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 + +#endif /* __nv_gf108_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf108/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gf108/nv_trim_hwref.h new file mode 100644 index 000000000..30fab536f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf108/nv_trim_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf108_trim_hwref_h__ +#define __nv_gf108_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gf108_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_bus_hwref.h new file mode 100644 index 000000000..4237f460e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_bus_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_bus_hwref_h__ +#define __nv_gf110_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 + +#endif /* __nv_gf110_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..020af6f40 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_ctxsw_prog_addendum_hwref_h__ +#define __nv_gf110_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gf110_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..77b845787 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_ctxsw_prog_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_ctxsw_prog_hwref_h__ +#define __nv_gf110_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab + +#endif /* __nv_gf110_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_fb_hwref.h new file mode 100644 index 000000000..512a09d4e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_fb_hwref_h__ +#define __nv_gf110_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gf110_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_fifo_hwref.h new file mode 100644 index 000000000..0942052ad --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_fifo_hwref.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_fifo_hwref_h__ +#define __nv_gf110_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 11:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*4) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 18:17 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 24:24 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 28:28 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_PBDMA_STATUS 0x26c0 + +#endif /* __nv_gf110_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_flush_hwref.h new file mode 100644 index 000000000..2b37c10ba --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_flush_hwref_h__ +#define __nv_gf110_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gf110_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..a652f3a38 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_graphics_nobundle_hwref.h @@ -0,0 +1,725 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_graphics_nobundle_hwref_h__ +#define __nv_gf110_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gf110_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_ltc_hwref.h new file mode 100644 index 000000000..8e09c07fc --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_ltc_hwref.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_ltc_hwref_h__ +#define __nv_gf110_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gf110_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_master_hwref.h new file mode 100644 index 000000000..169134429 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_master_hwref.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_master_hwref_h__ +#define __nv_gf110_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) + +#endif /* __nv_gf110_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_mmu_hwref.h new file mode 100644 index 000000000..6589abe74 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_mmu_hwref.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_mmu_hwref_h__ +#define __nv_gf110_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd + +#endif /* __nv_gf110_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_pbdma_hwref.h new file mode 100644 index 000000000..00d3cc783 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_pbdma_hwref.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_pbdma_hwref_h__ +#define __nv_gf110_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:12 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gf110_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..98ca51227 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_pri_ringmaster_hwref_h__ +#define __nv_gf110_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x121c60 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x121c58 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x121c5c +#define NV_PPRIV_MASTER_RING_COMMAND 0x121c4c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x121c48 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x121c50 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x121c74 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x121c78 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gf110_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..3b880d7db --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_pri_ringstation_sys_hwref_h__ +#define __nv_gf110_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gf110_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_proj_hwref.h new file mode 100644 index 000000000..d9b7a4edb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_proj_hwref.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_proj_hwref_h__ +#define __nv_gf110_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 4 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 4 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gf110_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..077879db5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_pwr_pri_hwref.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_pwr_pri_hwref_h__ +#define __nv_gf110_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gf110_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_ram_hwref.h new file mode 100644 index 000000000..844376a77 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_ram_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_ram_hwref_h__ +#define __nv_gf110_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 12 +#define NV_RAMRL_ENTRY_CHID (0*32+6):(0*32+0) + +#endif /* __nv_gf110_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_therm_hwref.h new file mode 100644 index 000000000..ba4ef644e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_therm_hwref_h__ +#define __nv_gf110_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gf110_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_timer_hwref.h new file mode 100644 index 000000000..aa9a31694 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_timer_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_timer_hwref_h__ +#define __nv_gf110_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gf110_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_top_hwref.h new file mode 100644 index 000000000..ac493c0cf --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_top_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_top_hwref_h__ +#define __nv_gf110_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 + +#endif /* __nv_gf110_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf110/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gf110/nv_trim_hwref.h new file mode 100644 index 000000000..fcfcdf75a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf110/nv_trim_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf110_trim_hwref_h__ +#define __nv_gf110_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gf110_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_bus_hwref.h new file mode 100644 index 000000000..f1c33cf65 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_bus_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_bus_hwref_h__ +#define __nv_gf114_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 + +#endif /* __nv_gf114_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..a4aa5e848 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_ctxsw_prog_addendum_hwref_h__ +#define __nv_gf114_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gf114_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..e8909108e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_ctxsw_prog_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_ctxsw_prog_hwref_h__ +#define __nv_gf114_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab + +#endif /* __nv_gf114_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_fb_hwref.h new file mode 100644 index 000000000..a4654c652 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_fb_hwref_h__ +#define __nv_gf114_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gf114_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_fifo_hwref.h new file mode 100644 index 000000000..bdb6b7955 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_fifo_hwref.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_fifo_hwref_h__ +#define __nv_gf114_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 11:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*4) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 18:17 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 24:24 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 28:28 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_PBDMA_STATUS 0x26c0 + +#endif /* __nv_gf114_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_flush_hwref.h new file mode 100644 index 000000000..c29f31a66 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_flush_hwref_h__ +#define __nv_gf114_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gf114_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..990d02838 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_graphics_nobundle_hwref.h @@ -0,0 +1,725 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_graphics_nobundle_hwref_h__ +#define __nv_gf114_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 + +#endif /* __nv_gf114_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_ltc_hwref.h new file mode 100644 index 000000000..1e68f46ae --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_ltc_hwref.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_ltc_hwref_h__ +#define __nv_gf114_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gf114_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_master_hwref.h new file mode 100644 index 000000000..3d67a95ea --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_master_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_master_hwref_h__ +#define __nv_gf114_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c + +#endif /* __nv_gf114_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_mmu_hwref.h new file mode 100644 index 000000000..9e4beed83 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_mmu_hwref.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_mmu_hwref_h__ +#define __nv_gf114_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd + +#endif /* __nv_gf114_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_pbdma_hwref.h new file mode 100644 index 000000000..8a6619c38 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_pbdma_hwref.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_pbdma_hwref_h__ +#define __nv_gf114_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:12 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gf114_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..a6273987c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_pri_ringmaster_hwref_h__ +#define __nv_gf114_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x121c60 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x121c58 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x121c5c +#define NV_PPRIV_MASTER_RING_COMMAND 0x121c4c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x121c48 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x121c50 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x121c74 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x121c78 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gf114_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..6607d4e7c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_pri_ringstation_sys_hwref_h__ +#define __nv_gf114_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gf114_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_proj_hwref.h new file mode 100644 index 000000000..d7a6f5716 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_proj_hwref.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_proj_hwref_h__ +#define __nv_gf114_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 4 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 4 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gf114_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..ea006409c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_pwr_pri_hwref.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_pwr_pri_hwref_h__ +#define __nv_gf114_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gf114_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_ram_hwref.h new file mode 100644 index 000000000..5b32452be --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_ram_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_ram_hwref_h__ +#define __nv_gf114_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 12 +#define NV_RAMRL_ENTRY_CHID (0*32+6):(0*32+0) + +#endif /* __nv_gf114_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_therm_hwref.h new file mode 100644 index 000000000..254642993 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_therm_hwref_h__ +#define __nv_gf114_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gf114_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_timer_hwref.h new file mode 100644 index 000000000..a3cc7f234 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_timer_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_timer_hwref_h__ +#define __nv_gf114_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gf114_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_top_hwref.h new file mode 100644 index 000000000..fe6a89c93 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_top_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_top_hwref_h__ +#define __nv_gf114_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 + +#endif /* __nv_gf114_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf114/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gf114/nv_trim_hwref.h new file mode 100644 index 000000000..b21f6a77a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf114/nv_trim_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf114_trim_hwref_h__ +#define __nv_gf114_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gf114_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_bus_hwref.h new file mode 100644 index 000000000..ae9ee73bd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_bus_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_bus_hwref_h__ +#define __nv_gf116_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 + +#endif /* __nv_gf116_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..920421cb2 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_ctxsw_prog_addendum_hwref_h__ +#define __nv_gf116_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gf116_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..5ddbbd489 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_ctxsw_prog_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_ctxsw_prog_hwref_h__ +#define __nv_gf116_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab + +#endif /* __nv_gf116_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_fb_hwref.h new file mode 100644 index 000000000..09f8fd750 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_fb_hwref_h__ +#define __nv_gf116_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gf116_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_fifo_hwref.h new file mode 100644 index 000000000..2f531290a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_fifo_hwref.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_fifo_hwref_h__ +#define __nv_gf116_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 11:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*4) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 18:17 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 24:24 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 28:28 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_PBDMA_STATUS 0x26c0 + +#endif /* __nv_gf116_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_flush_hwref.h new file mode 100644 index 000000000..6485c86de --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_flush_hwref_h__ +#define __nv_gf116_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gf116_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..72f174c5a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_graphics_nobundle_hwref.h @@ -0,0 +1,725 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_graphics_nobundle_hwref_h__ +#define __nv_gf116_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 + +#endif /* __nv_gf116_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_ltc_hwref.h new file mode 100644 index 000000000..4792ea65b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_ltc_hwref.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_ltc_hwref_h__ +#define __nv_gf116_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gf116_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_master_hwref.h new file mode 100644 index 000000000..a95986c2c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_master_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_master_hwref_h__ +#define __nv_gf116_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c + +#endif /* __nv_gf116_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_mmu_hwref.h new file mode 100644 index 000000000..abb96b92d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_mmu_hwref.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_mmu_hwref_h__ +#define __nv_gf116_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd + +#endif /* __nv_gf116_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_pbdma_hwref.h new file mode 100644 index 000000000..5a7c486ed --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_pbdma_hwref.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_pbdma_hwref_h__ +#define __nv_gf116_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:12 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gf116_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..7de10b3ff --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_pri_ringmaster_hwref_h__ +#define __nv_gf116_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x121c60 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x121c58 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x121c5c +#define NV_PPRIV_MASTER_RING_COMMAND 0x121c4c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x121c48 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x121c50 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x121c74 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x121c78 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gf116_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..5bf9a6226 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_pri_ringstation_sys_hwref_h__ +#define __nv_gf116_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gf116_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_proj_hwref.h new file mode 100644 index 000000000..c5f3b2fdd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_proj_hwref.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_proj_hwref_h__ +#define __nv_gf116_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 4 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 4 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gf116_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..71134426e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_pwr_pri_hwref.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_pwr_pri_hwref_h__ +#define __nv_gf116_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gf116_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_ram_hwref.h new file mode 100644 index 000000000..edc2cb553 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_ram_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_ram_hwref_h__ +#define __nv_gf116_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 12 +#define NV_RAMRL_ENTRY_CHID (0*32+6):(0*32+0) + +#endif /* __nv_gf116_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_therm_hwref.h new file mode 100644 index 000000000..55749ec48 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_therm_hwref_h__ +#define __nv_gf116_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gf116_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_timer_hwref.h new file mode 100644 index 000000000..2c5935dcd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_timer_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_timer_hwref_h__ +#define __nv_gf116_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gf116_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_top_hwref.h new file mode 100644 index 000000000..6ec5cd7a5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_top_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_top_hwref_h__ +#define __nv_gf116_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 + +#endif /* __nv_gf116_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf116/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gf116/nv_trim_hwref.h new file mode 100644 index 000000000..2d8ca083d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf116/nv_trim_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf116_trim_hwref_h__ +#define __nv_gf116_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gf116_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_bus_hwref.h new file mode 100644 index 000000000..aad0ce4ad --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_bus_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_bus_hwref_h__ +#define __nv_gf117_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 + +#endif /* __nv_gf117_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..c60ec880e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_ctxsw_prog_addendum_hwref_h__ +#define __nv_gf117_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gf117_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..eb86f2156 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_ctxsw_prog_hwref.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_ctxsw_prog_hwref_h__ +#define __nv_gf117_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab + +#endif /* __nv_gf117_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_fb_hwref.h new file mode 100644 index 000000000..49deae3a0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_fb_hwref_h__ +#define __nv_gf117_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gf117_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_fifo_hwref.h new file mode 100644 index 000000000..a419a41f6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_fifo_hwref.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_fifo_hwref_h__ +#define __nv_gf117_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 11:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*4) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 18:17 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 24:24 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 28:28 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 + +#endif /* __nv_gf117_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_flush_hwref.h new file mode 100644 index 000000000..d568b11ab --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_flush_hwref_h__ +#define __nv_gf117_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gf117_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..d38e8f302 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_graphics_nobundle_hwref.h @@ -0,0 +1,795 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_graphics_nobundle_hwref_h__ +#define __nv_gf117_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x218 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x324 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gf117_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_ltc_hwref.h new file mode 100644 index 000000000..619235327 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_ltc_hwref.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_ltc_hwref_h__ +#define __nv_gf117_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gf117_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_master_hwref.h new file mode 100644 index 000000000..a82bbbdd9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_master_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_master_hwref_h__ +#define __nv_gf117_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c + +#endif /* __nv_gf117_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_mmu_hwref.h new file mode 100644 index 000000000..8e5a2b740 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_mmu_hwref.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_mmu_hwref_h__ +#define __nv_gf117_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd + +#endif /* __nv_gf117_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_pbdma_hwref.h new file mode 100644 index 000000000..67a422079 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_pbdma_hwref.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_pbdma_hwref_h__ +#define __nv_gf117_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 1 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:12 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 1 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gf117_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..e388257fa --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_pri_ringmaster_hwref_h__ +#define __nv_gf117_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x121c60 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x121c58 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x121c5c +#define NV_PPRIV_MASTER_RING_COMMAND 0x121c4c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x121c48 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x121c50 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x121c74 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x121c78 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gf117_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..391d09fd5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_pri_ringstation_sys_hwref_h__ +#define __nv_gf117_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gf117_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_proj_hwref.h new file mode 100644 index 000000000..d2f9c191a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_proj_hwref_h__ +#define __nv_gf117_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 1 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 1 +#define NV_SCAL_LITTER_NUM_GPCS 1 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gf117_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..2125a3fbd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_pwr_pri_hwref.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_pwr_pri_hwref_h__ +#define __nv_gf117_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a8a0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10a8a4+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gf117_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_ram_hwref.h new file mode 100644 index 000000000..305ee9e61 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_ram_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_ram_hwref_h__ +#define __nv_gf117_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 12 +#define NV_RAMRL_ENTRY_CHID (0*32+6):(0*32+0) + +#endif /* __nv_gf117_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_therm_hwref.h new file mode 100644 index 000000000..31488edb5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_therm_hwref_h__ +#define __nv_gf117_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gf117_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_timer_hwref.h new file mode 100644 index 000000000..618dcf3c7 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_timer_hwref_h__ +#define __nv_gf117_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gf117_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_top_hwref.h new file mode 100644 index 000000000..306789381 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_top_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_top_hwref_h__ +#define __nv_gf117_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 + +#endif /* __nv_gf117_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf117/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gf117/nv_trim_hwref.h new file mode 100644 index 000000000..49bae6e9c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf117/nv_trim_hwref.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf117_trim_hwref_h__ +#define __nv_gf117_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gf117_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_bus_hwref.h new file mode 100644 index 000000000..ffa950b50 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_bus_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_bus_hwref_h__ +#define __nv_gf119_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 + +#endif /* __nv_gf119_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..0162766bb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_ctxsw_prog_addendum_hwref_h__ +#define __nv_gf119_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gf119_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..5da7673b9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_ctxsw_prog_hwref.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_ctxsw_prog_hwref_h__ +#define __nv_gf119_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab + +#endif /* __nv_gf119_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_fb_hwref.h new file mode 100644 index 000000000..ad215314b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_fb_hwref_h__ +#define __nv_gf119_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gf119_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_fifo_hwref.h new file mode 100644 index 000000000..d54f042a0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_fifo_hwref.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_fifo_hwref_h__ +#define __nv_gf119_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 11:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*4) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 18:17 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 24:24 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 28:28 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 + +#endif /* __nv_gf119_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_flush_hwref.h new file mode 100644 index 000000000..74df03a96 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_flush_hwref_h__ +#define __nv_gf119_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gf119_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..123e3f480 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_graphics_nobundle_hwref.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_graphics_nobundle_hwref_h__ +#define __nv_gf119_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gf119_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_ltc_hwref.h new file mode 100644 index 000000000..c115f7aa7 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_ltc_hwref.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_ltc_hwref_h__ +#define __nv_gf119_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gf119_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_master_hwref.h new file mode 100644 index 000000000..245ac54d7 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_master_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_master_hwref_h__ +#define __nv_gf119_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c + +#endif /* __nv_gf119_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_mmu_hwref.h new file mode 100644 index 000000000..60d4ee0de --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_mmu_hwref.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_mmu_hwref_h__ +#define __nv_gf119_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd + +#endif /* __nv_gf119_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_pbdma_hwref.h new file mode 100644 index 000000000..896470046 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_pbdma_hwref.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_pbdma_hwref_h__ +#define __nv_gf119_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 1 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:12 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 1 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gf119_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..b7f45ca8b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_pri_ringmaster_hwref_h__ +#define __nv_gf119_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x121c60 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x121c58 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x121c5c +#define NV_PPRIV_MASTER_RING_COMMAND 0x121c4c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x121c48 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x121c50 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x121c74 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x121c78 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gf119_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..afd2452c5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_pri_ringstation_sys_hwref_h__ +#define __nv_gf119_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gf119_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_proj_hwref.h new file mode 100644 index 000000000..f40ebaa09 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_proj_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_proj_hwref_h__ +#define __nv_gf119_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 1 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 1 +#define NV_SCAL_LITTER_NUM_GPCS 1 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gf119_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..481609f77 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_pwr_pri_hwref.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_pwr_pri_hwref_h__ +#define __nv_gf119_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a8a0+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10a8a4+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gf119_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_ram_hwref.h new file mode 100644 index 000000000..bd8ebccc2 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_ram_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_ram_hwref_h__ +#define __nv_gf119_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 12 +#define NV_RAMRL_ENTRY_CHID (0*32+6):(0*32+0) + +#endif /* __nv_gf119_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_therm_hwref.h new file mode 100644 index 000000000..fcd645228 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_therm_hwref_h__ +#define __nv_gf119_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gf119_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_timer_hwref.h new file mode 100644 index 000000000..1e0a212be --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_timer_hwref_h__ +#define __nv_gf119_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gf119_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_top_hwref.h new file mode 100644 index 000000000..01a523c67 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_top_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_top_hwref_h__ +#define __nv_gf119_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 + +#endif /* __nv_gf119_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gf119/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gf119/nv_trim_hwref.h new file mode 100644 index 000000000..d0ea9080a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gf119/nv_trim_hwref.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gf119_trim_hwref_h__ +#define __nv_gf119_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gf119_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_bus_hwref.h new file mode 100644 index 000000000..72a78dd46 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_bus_hwref_h__ +#define __nv_gk104_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gk104_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..2311b7e1b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_ce2_pri_hwref_h__ +#define __nv_gk104_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gk104_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..438e29515 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_ctxsw_prog_addendum_hwref_h__ +#define __nv_gk104_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gk104_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..4eae39c4c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_ctxsw_prog_hwref_h__ +#define __nv_gk104_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 0:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_NUM_SMPC_QUADRANTS 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 5 + +#endif /* __nv_gk104_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_fb_hwref.h new file mode 100644 index 000000000..256590329 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_fb_hwref_h__ +#define __nv_gk104_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gk104_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_fifo_hwref.h new file mode 100644 index 000000000..4881bd445 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_fifo_hwref.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_fifo_hwref_h__ +#define __nv_gk104_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_RUNLIST 19:16 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_RUNLIST_TIMESLICE(i) (0x2310+(i)*4) +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PFIFO_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 3 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 8 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 3 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gk104_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_flush_hwref.h new file mode 100644 index 000000000..fe82aba9d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_flush_hwref_h__ +#define __nv_gk104_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gk104_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..ec4582201 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_graphics_nobundle_hwref.h @@ -0,0 +1,854 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_graphics_nobundle_hwref_h__ +#define __nv_gk104_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x600 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x272 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15 27:27 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15_EN 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_SMKEPLER_LP 12 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x218 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x648 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_LOCKBOOST_SIZE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK 0x419ec8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT 11:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gk104_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_ltc_hwref.h new file mode 100644 index 000000000..4a4b5a9e8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_ltc_hwref.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_ltc_hwref_h__ +#define __nv_gk104_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140828 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142828 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e828 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gk104_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_master_hwref.h new file mode 100644 index 000000000..c42ae8ffd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_master_hwref.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_master_hwref_h__ +#define __nv_gk104_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gk104_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_mmu_hwref.h new file mode 100644 index 000000000..4a0a80fd4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_mmu_hwref_h__ +#define __nv_gk104_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gk104_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_pbdma_hwref.h new file mode 100644 index 000000000..7f4e87c24 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_pbdma_hwref.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_pbdma_hwref_h__ +#define __nv_gk104_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gk104_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..9c8fee649 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_pri_ringmaster_hwref_h__ +#define __nv_gk104_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gk104_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..49ee0dc49 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_pri_ringstation_sys_hwref_h__ +#define __nv_gk104_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gk104_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_proj_hwref.h new file mode 100644 index 000000000..47b3d1549 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_proj_hwref_h__ +#define __nv_gk104_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 4 +#define NV_SCAL_LITTER_NUM_GPCS 4 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gk104_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..c6e239267 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_pwr_pri_hwref.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_pwr_pri_hwref_h__ +#define __nv_gk104_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gk104_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_ram_hwref.h new file mode 100644 index 000000000..8ad163df9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_ram_hwref.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_ram_hwref_h__ +#define __nv_gk104_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gk104_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_therm_hwref.h new file mode 100644 index 000000000..6c0bb5323 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_therm_hwref_h__ +#define __nv_gk104_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gk104_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_timer_hwref.h new file mode 100644 index 000000000..18757a6aa --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_timer_hwref_h__ +#define __nv_gk104_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gk104_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_top_hwref.h new file mode 100644 index 000000000..1dee76bd3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_top_hwref_h__ +#define __nv_gk104_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gk104_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk104/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gk104/nv_trim_hwref.h new file mode 100644 index 000000000..c34257d0d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk104/nv_trim_hwref.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk104_trim_hwref_h__ +#define __nv_gk104_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gk104_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_bus_hwref.h new file mode 100644 index 000000000..234a86546 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_bus_hwref_h__ +#define __nv_gk106_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gk106_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..fe45cdd3a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_ce2_pri_hwref_h__ +#define __nv_gk106_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gk106_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..18d24172e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_ctxsw_prog_addendum_hwref_h__ +#define __nv_gk106_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gk106_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..dd8f4fb1c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_ctxsw_prog_hwref_h__ +#define __nv_gk106_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 0:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_NUM_SMPC_QUADRANTS 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 5 + +#endif /* __nv_gk106_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_fb_hwref.h new file mode 100644 index 000000000..66c0d9de7 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_fb_hwref_h__ +#define __nv_gk106_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gk106_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_fifo_hwref.h new file mode 100644 index 000000000..22c743aca --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_fifo_hwref.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_fifo_hwref_h__ +#define __nv_gk106_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_RUNLIST 19:16 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_RUNLIST_TIMESLICE(i) (0x2310+(i)*4) +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PFIFO_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 3 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 8 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 3 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gk106_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_flush_hwref.h new file mode 100644 index 000000000..50036de4d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_flush_hwref_h__ +#define __nv_gk106_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gk106_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..ab5941680 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_graphics_nobundle_hwref.h @@ -0,0 +1,854 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_graphics_nobundle_hwref_h__ +#define __nv_gk106_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x600 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x272 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15 27:27 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15_EN 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_SMKEPLER_LP 12 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x218 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x648 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_LOCKBOOST_SIZE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK 0x419ec8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT 11:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gk106_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_ltc_hwref.h new file mode 100644 index 000000000..729e2b53f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_ltc_hwref.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_ltc_hwref_h__ +#define __nv_gk106_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140828 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142828 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e828 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gk106_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_master_hwref.h new file mode 100644 index 000000000..fa9772d56 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_master_hwref.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_master_hwref_h__ +#define __nv_gk106_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gk106_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_mmu_hwref.h new file mode 100644 index 000000000..2858cb7cb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_mmu_hwref_h__ +#define __nv_gk106_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gk106_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_pbdma_hwref.h new file mode 100644 index 000000000..df825da2c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_pbdma_hwref.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_pbdma_hwref_h__ +#define __nv_gk106_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gk106_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..e54843699 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_pri_ringmaster_hwref_h__ +#define __nv_gk106_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gk106_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..768daad5d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_pri_ringstation_sys_hwref_h__ +#define __nv_gk106_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gk106_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_proj_hwref.h new file mode 100644 index 000000000..5ff213de4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_proj_hwref_h__ +#define __nv_gk106_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 4 +#define NV_SCAL_LITTER_NUM_GPCS 4 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gk106_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..32025462b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_pwr_pri_hwref.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_pwr_pri_hwref_h__ +#define __nv_gk106_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gk106_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_ram_hwref.h new file mode 100644 index 000000000..58e3054bb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_ram_hwref.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_ram_hwref_h__ +#define __nv_gk106_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gk106_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_therm_hwref.h new file mode 100644 index 000000000..8127e764b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_therm_hwref_h__ +#define __nv_gk106_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gk106_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_timer_hwref.h new file mode 100644 index 000000000..62ad31ef6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_timer_hwref_h__ +#define __nv_gk106_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gk106_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_top_hwref.h new file mode 100644 index 000000000..663aeb59d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_top_hwref_h__ +#define __nv_gk106_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gk106_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk106/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gk106/nv_trim_hwref.h new file mode 100644 index 000000000..d9a604231 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk106/nv_trim_hwref.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk106_trim_hwref_h__ +#define __nv_gk106_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gk106_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_bus_hwref.h new file mode 100644 index 000000000..77b0683da --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_bus_hwref_h__ +#define __nv_gk107_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gk107_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..6fd5df5ef --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_ce2_pri_hwref_h__ +#define __nv_gk107_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gk107_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..20c34f168 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_ctxsw_prog_addendum_hwref_h__ +#define __nv_gk107_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gk107_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..881d74a9e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_ctxsw_prog_hwref_h__ +#define __nv_gk107_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 0:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_NUM_SMPC_QUADRANTS 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 5 + +#endif /* __nv_gk107_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_fb_hwref.h new file mode 100644 index 000000000..932014804 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_fb_hwref_h__ +#define __nv_gk107_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gk107_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_fifo_hwref.h new file mode 100644 index 000000000..6098b5022 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_fifo_hwref.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_fifo_hwref_h__ +#define __nv_gk107_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_RUNLIST 19:16 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_RUNLIST_TIMESLICE(i) (0x2310+(i)*4) +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PFIFO_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 3 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 8 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 3 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gk107_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_flush_hwref.h new file mode 100644 index 000000000..216e1998b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_flush_hwref_h__ +#define __nv_gk107_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gk107_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..a23cb8852 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_graphics_nobundle_hwref.h @@ -0,0 +1,854 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_graphics_nobundle_hwref_h__ +#define __nv_gk107_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x600 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x272 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15 27:27 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15_EN 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_SMKEPLER_LP 12 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x218 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x648 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_LOCKBOOST_SIZE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK 0x419ec8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT 11:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gk107_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_ltc_hwref.h new file mode 100644 index 000000000..7b0ddd467 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_ltc_hwref.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_ltc_hwref_h__ +#define __nv_gk107_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140828 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142828 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e828 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gk107_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_master_hwref.h new file mode 100644 index 000000000..99fca6348 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_master_hwref.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_master_hwref_h__ +#define __nv_gk107_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gk107_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_mmu_hwref.h new file mode 100644 index 000000000..956f003ce --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_mmu_hwref_h__ +#define __nv_gk107_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gk107_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_pbdma_hwref.h new file mode 100644 index 000000000..297d6ca6c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_pbdma_hwref.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_pbdma_hwref_h__ +#define __nv_gk107_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gk107_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..737da0345 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_pri_ringmaster_hwref_h__ +#define __nv_gk107_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gk107_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..8284284cd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_pri_ringstation_sys_hwref_h__ +#define __nv_gk107_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gk107_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_proj_hwref.h new file mode 100644 index 000000000..d83001de0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_proj_hwref_h__ +#define __nv_gk107_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 4 +#define NV_SCAL_LITTER_NUM_GPCS 4 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gk107_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..56f55b2fc --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_pwr_pri_hwref.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_pwr_pri_hwref_h__ +#define __nv_gk107_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gk107_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_ram_hwref.h new file mode 100644 index 000000000..96c47d685 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_ram_hwref.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_ram_hwref_h__ +#define __nv_gk107_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gk107_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_therm_hwref.h new file mode 100644 index 000000000..c0c0debfc --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_therm_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_therm_hwref_h__ +#define __nv_gk107_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gk107_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_timer_hwref.h new file mode 100644 index 000000000..b52f5dca8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_timer_hwref_h__ +#define __nv_gk107_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gk107_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_top_hwref.h new file mode 100644 index 000000000..fd390e965 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_top_hwref_h__ +#define __nv_gk107_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gk107_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk107/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gk107/nv_trim_hwref.h new file mode 100644 index 000000000..04b640926 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk107/nv_trim_hwref.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk107_trim_hwref_h__ +#define __nv_gk107_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 + +#endif /* __nv_gk107_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_bus_hwref.h new file mode 100644 index 000000000..e09b3402d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_bus_hwref_h__ +#define __nv_gk110_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gk110_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..5de688183 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_ce2_pri_hwref_h__ +#define __nv_gk110_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gk110_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..9ad4f06c0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_ctxsw_prog_addendum_hwref_h__ +#define __nv_gk110_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gk110_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..eac82268c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_ctxsw_prog_hwref_h__ +#define __nv_gk110_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 0:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_NUM_SMPC_QUADRANTS 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 5 + +#endif /* __nv_gk110_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_fb_hwref.h new file mode 100644 index 000000000..e6af3c9f0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_fb_hwref_h__ +#define __nv_gk110_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gk110_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_fifo_hwref.h new file mode 100644 index 000000000..d2eea4574 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_fifo_hwref.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_fifo_hwref_h__ +#define __nv_gk110_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_RUNLIST 19:16 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_RUNLIST_TIMESLICE(i) (0x2310+(i)*4) +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PFIFO_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 3 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 8 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 3 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gk110_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_flush_hwref.h new file mode 100644 index 000000000..49d35426a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_flush_hwref_h__ +#define __nv_gk110_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gk110_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..94275ba55 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_graphics_nobundle_hwref.h @@ -0,0 +1,856 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_graphics_nobundle_hwref_h__ +#define __nv_gk110_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x7c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x5a2 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15 27:27 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15_EN 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_SMKEPLER_LP 12 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x218 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x648 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_LOCKBOOST_SIZE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK 0x419ec8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT 11:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gk110_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_ltc_hwref.h new file mode 100644 index 000000000..8ae2201c2 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_ltc_hwref.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_ltc_hwref_h__ +#define __nv_gk110_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140828 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142828 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e828 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gk110_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_master_hwref.h new file mode 100644 index 000000000..16b7ffb47 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_master_hwref.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_master_hwref_h__ +#define __nv_gk110_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gk110_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_mmu_hwref.h new file mode 100644 index 000000000..ebcf93379 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_mmu_hwref_h__ +#define __nv_gk110_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gk110_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_pbdma_hwref.h new file mode 100644 index 000000000..68719d2cb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_pbdma_hwref.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_pbdma_hwref_h__ +#define __nv_gk110_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gk110_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..932b5dafe --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_pri_ringmaster_hwref_h__ +#define __nv_gk110_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gk110_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..28a8e3d5c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_pri_ringstation_sys_hwref_h__ +#define __nv_gk110_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gk110_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_proj_hwref.h new file mode 100644 index 000000000..cafb592e6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_proj_hwref_h__ +#define __nv_gk110_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 5 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 3 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gk110_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..d02045939 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_pwr_pri_hwref.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_pwr_pri_hwref_h__ +#define __nv_gk110_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gk110_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_ram_hwref.h new file mode 100644 index 000000000..39bbf72df --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_ram_hwref.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_ram_hwref_h__ +#define __nv_gk110_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gk110_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_therm_hwref.h new file mode 100644 index 000000000..5a311c89a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_therm_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_therm_hwref_h__ +#define __nv_gk110_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gk110_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_timer_hwref.h new file mode 100644 index 000000000..63238542c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_timer_hwref_h__ +#define __nv_gk110_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gk110_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_top_hwref.h new file mode 100644 index 000000000..ff4e71a10 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_top_hwref_h__ +#define __nv_gk110_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gk110_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..bdcd0d287 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_trim_addendum_hwref_h__ +#define __nv_gk110_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gk110_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110/nv_trim_hwref.h new file mode 100644 index 000000000..b9bc3a45f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110/nv_trim_hwref.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110_trim_hwref_h__ +#define __nv_gk110_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gk110_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_bus_hwref.h new file mode 100644 index 000000000..348898c65 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_bus_hwref_h__ +#define __nv_gk110b_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gk110b_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..d6015ddb5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ce2_pri_hwref_h__ +#define __nv_gk110b_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gk110b_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..742a9f0bd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ctxsw_prog_addendum_hwref_h__ +#define __nv_gk110b_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gk110b_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..082450ada --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ctxsw_prog_hwref_h__ +#define __nv_gk110b_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 0:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_NUM_SMPC_QUADRANTS 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 5 + +#endif /* __nv_gk110b_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_fb_hwref.h new file mode 100644 index 000000000..24b5a2201 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_fb_hwref_h__ +#define __nv_gk110b_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gk110b_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_fifo_hwref.h new file mode 100644 index 000000000..b718bb508 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_fifo_hwref.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_fifo_hwref_h__ +#define __nv_gk110b_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_RUNLIST 19:16 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_RUNLIST_TIMESLICE(i) (0x2310+(i)*4) +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PFIFO_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 3 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 8 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 3 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gk110b_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_flush_hwref.h new file mode 100644 index 000000000..55e5a26a4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_flush_hwref_h__ +#define __nv_gk110b_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gk110b_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..fdd4f4403 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_graphics_nobundle_hwref.h @@ -0,0 +1,856 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_graphics_nobundle_hwref_h__ +#define __nv_gk110b_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x7c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x5a2 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15 27:27 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15_EN 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_SMKEPLER_LP 12 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x218 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x648 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_LOCKBOOST_SIZE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK 0x419ec8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT 11:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gk110b_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ltc_hwref.h new file mode 100644 index 000000000..777a260ea --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ltc_hwref.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ltc_hwref_h__ +#define __nv_gk110b_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140828 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142828 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e828 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gk110b_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_master_hwref.h new file mode 100644 index 000000000..b75399f99 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_master_hwref.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_master_hwref_h__ +#define __nv_gk110b_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gk110b_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_mmu_hwref.h new file mode 100644 index 000000000..73ecfef6e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_mmu_hwref_h__ +#define __nv_gk110b_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gk110b_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pbdma_hwref.h new file mode 100644 index 000000000..7118fb0ef --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pbdma_hwref.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_pbdma_hwref_h__ +#define __nv_gk110b_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gk110b_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..e0afee067 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_pri_ringmaster_hwref_h__ +#define __nv_gk110b_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gk110b_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..835889f63 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_pri_ringstation_sys_hwref_h__ +#define __nv_gk110b_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gk110b_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_proj_hwref.h new file mode 100644 index 000000000..f181a9849 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_proj_hwref_h__ +#define __nv_gk110b_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 5 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 3 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gk110b_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..d3cbbf97f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pwr_pri_hwref.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_pwr_pri_hwref_h__ +#define __nv_gk110b_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gk110b_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ram_hwref.h new file mode 100644 index 000000000..e29982b08 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ram_hwref.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ram_hwref_h__ +#define __nv_gk110b_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gk110b_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_therm_hwref.h new file mode 100644 index 000000000..9b9551e68 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_therm_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_therm_hwref_h__ +#define __nv_gk110b_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gk110b_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_timer_hwref.h new file mode 100644 index 000000000..d6a465150 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_timer_hwref_h__ +#define __nv_gk110b_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gk110b_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_top_hwref.h new file mode 100644 index 000000000..d4df634d3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_top_hwref_h__ +#define __nv_gk110b_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gk110b_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..95cc09dfd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_trim_addendum_hwref_h__ +#define __nv_gk110b_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gk110b_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_hwref.h new file mode 100644 index 000000000..25dd3e60a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_hwref.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_trim_hwref_h__ +#define __nv_gk110b_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gk110b_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_bus_hwref.h new file mode 100644 index 000000000..1b4631dd4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_bus_hwref_h__ +#define __nv_gk208_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gk208_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..8964c2dc1 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_ce2_pri_hwref_h__ +#define __nv_gk208_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gk208_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..bb4dbb8bf --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_ctxsw_prog_addendum_hwref_h__ +#define __nv_gk208_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gk208_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..882a5d207 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_ctxsw_prog_hwref_h__ +#define __nv_gk208_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 0:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_NUM_SMPC_QUADRANTS 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 5 + +#endif /* __nv_gk208_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_fb_hwref.h new file mode 100644 index 000000000..fbd1f2597 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_fb_hwref.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_fb_hwref_h__ +#define __nv_gk208_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 +#define NV_PFB_PRI_MMU_VPR_INFO 0x100cd0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX 1:0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_LO 0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_HI 1 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_LO 2 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_HI 3 +#define NV_PFB_PRI_MMU_VPR_INFO_FETCH 2:2 + +#endif /* __nv_gk208_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_fifo_hwref.h new file mode 100644 index 000000000..abd54e87d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_fifo_hwref.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_fifo_hwref_h__ +#define __nv_gk208_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x400 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x400 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_RUNLIST 19:16 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_RUNLIST_TIMESLICE(i) (0x2310+(i)*4) +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PFIFO_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 2 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 7 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 2 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gk208_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_flush_hwref.h new file mode 100644 index 000000000..62bfb48c0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_flush_hwref_h__ +#define __nv_gk208_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gk208_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..e1c2abfac --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_graphics_nobundle_hwref.h @@ -0,0 +1,880 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_graphics_nobundle_hwref_h__ +#define __nv_gk208_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_FE_GI 21:21 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x404194 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT 0x409008 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE 0x40900c +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK 0x409018 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST 0x40901c +#define NV_PGRAPH_PRI_FECS_FALCON_CURCTX 0x409050 +#define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX 0x409054 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1 0x409090 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 31:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD 0x409200 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC 3:0 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX 12:8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA 0x40920c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x200 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0xc2 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15 27:27 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15_EN 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_SMKEPLER_LP 12 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x218 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x648 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR 0x41a0ac +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB 5:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB 11:6 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_EXT 11:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_LOCKBOOST_SIZE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK 0x419ec8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT 11:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gk208_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_ltc_hwref.h new file mode 100644 index 000000000..cef834a06 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_ltc_hwref.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_ltc_hwref_h__ +#define __nv_gk208_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140828 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e828 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gk208_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_master_hwref.h new file mode 100644 index 000000000..51b23482e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_master_hwref.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_master_hwref_h__ +#define __nv_gk208_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gk208_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_mmu_hwref.h new file mode 100644 index 000000000..9630535d9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_mmu_hwref_h__ +#define __nv_gk208_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gk208_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_pbdma_hwref.h new file mode 100644 index 000000000..23a60c045 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_pbdma_hwref.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_pbdma_hwref_h__ +#define __nv_gk208_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 2 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 2 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gk208_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..d719dec5f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_pri_ringmaster_hwref_h__ +#define __nv_gk208_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gk208_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..dca1c3a60 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_pri_ringstation_sys_hwref_h__ +#define __nv_gk208_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gk208_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_proj_hwref.h new file mode 100644 index 000000000..12a9e8a4f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_proj_hwref_h__ +#define __nv_gk208_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 2 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 1 +#define NV_SCAL_LITTER_NUM_GPCS 1 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gk208_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..f809950a6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_pwr_pri_hwref.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_pwr_pri_hwref_h__ +#define __nv_gk208_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a480 +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a450+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 12 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gk208_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_ram_hwref.h new file mode 100644 index 000000000..1158822de --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_ram_hwref.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_ram_hwref_h__ +#define __nv_gk208_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gk208_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_therm_hwref.h new file mode 100644 index 000000000..8bba0df48 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_therm_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_therm_hwref_h__ +#define __nv_gk208_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gk208_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_timer_hwref.h new file mode 100644 index 000000000..14a077b7b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_timer_hwref_h__ +#define __nv_gk208_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gk208_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_top_hwref.h new file mode 100644 index 000000000..cd8cc155f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_top_hwref_h__ +#define __nv_gk208_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gk208_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..afa627069 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_trim_addendum_hwref_h__ +#define __nv_gk208_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gk208_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208/nv_trim_hwref.h new file mode 100644 index 000000000..64353a985 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208/nv_trim_hwref.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208_trim_hwref_h__ +#define __nv_gk208_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gk208_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_bus_hwref.h new file mode 100644 index 000000000..e02170a07 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_bus_hwref_h__ +#define __nv_gk208b_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gk208b_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..b66b9f58e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_ce2_pri_hwref_h__ +#define __nv_gk208b_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gk208b_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..abc9b647a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_ctxsw_prog_addendum_hwref_h__ +#define __nv_gk208b_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gk208b_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..23418625f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_ctxsw_prog_hwref_h__ +#define __nv_gk208b_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 0:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_NUM_SMPC_QUADRANTS 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 5 + +#endif /* __nv_gk208b_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_fb_hwref.h new file mode 100644 index 000000000..8b1e7ef49 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_fb_hwref.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_fb_hwref_h__ +#define __nv_gk208b_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 +#define NV_PFB_PRI_MMU_VPR_INFO 0x100cd0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX 1:0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_LO 0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_HI 1 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_LO 2 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_HI 3 +#define NV_PFB_PRI_MMU_VPR_INFO_FETCH 2:2 + +#endif /* __nv_gk208b_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_fifo_hwref.h new file mode 100644 index 000000000..f2640a1f7 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_fifo_hwref.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_fifo_hwref_h__ +#define __nv_gk208b_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x400 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x400 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_RUNLIST 19:16 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 6 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_RUNLIST_TIMESLICE(i) (0x2310+(i)*4) +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PFIFO_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 2 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 7 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 2 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gk208b_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_flush_hwref.h new file mode 100644 index 000000000..db03e86c6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_flush_hwref_h__ +#define __nv_gk208b_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gk208b_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..66e9856b6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_graphics_nobundle_hwref.h @@ -0,0 +1,880 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_graphics_nobundle_hwref_h__ +#define __nv_gk208b_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_FE_GI 21:21 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x404194 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT 0x409008 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE 0x40900c +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK 0x409018 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST 0x40901c +#define NV_PGRAPH_PRI_FECS_FALCON_CURCTX 0x409050 +#define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX 0x409054 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1 0x409090 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 31:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD 0x409200 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC 3:0 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX 12:8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA 0x40920c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x200 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0xc2 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15 27:27 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15_EN 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_SMKEPLER_LP 12 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x218 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x648 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR 0x41a0ac +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB 5:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB 11:6 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_EXT 11:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_LOCKBOOST_SIZE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK 0x419ec8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT 11:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gk208b_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ltc_hwref.h new file mode 100644 index 000000000..8d7cba6e4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ltc_hwref.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_ltc_hwref_h__ +#define __nv_gk208b_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140828 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e828 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gk208b_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_master_hwref.h new file mode 100644 index 000000000..3f75b8c19 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_master_hwref.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_master_hwref_h__ +#define __nv_gk208b_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gk208b_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_mmu_hwref.h new file mode 100644 index 000000000..806dd798c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_mmu_hwref_h__ +#define __nv_gk208b_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gk208b_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_pbdma_hwref.h new file mode 100644 index 000000000..420e18410 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_pbdma_hwref.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_pbdma_hwref_h__ +#define __nv_gk208b_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 2 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 2 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gk208b_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..d3316e654 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_pri_ringmaster_hwref_h__ +#define __nv_gk208b_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gk208b_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..e27b8c65e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_pri_ringstation_sys_hwref_h__ +#define __nv_gk208b_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gk208b_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_proj_hwref.h new file mode 100644 index 000000000..03d2b982e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_proj_hwref_h__ +#define __nv_gk208b_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 2 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 1 +#define NV_SCAL_LITTER_NUM_GPCS 1 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gk208b_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..f9f173f44 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_pwr_pri_hwref.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_pwr_pri_hwref_h__ +#define __nv_gk208b_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a480 +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a450+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 12 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gk208b_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ram_hwref.h new file mode 100644 index 000000000..c044ddf35 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_ram_hwref.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_ram_hwref_h__ +#define __nv_gk208b_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gk208b_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_therm_hwref.h new file mode 100644 index 000000000..8837f2bf6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_therm_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_therm_hwref_h__ +#define __nv_gk208b_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gk208b_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_timer_hwref.h new file mode 100644 index 000000000..b53f12d85 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_timer_hwref_h__ +#define __nv_gk208b_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gk208b_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_top_hwref.h new file mode 100644 index 000000000..00ed04dc3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_top_hwref_h__ +#define __nv_gk208b_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gk208b_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..73fb735e6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_trim_addendum_hwref_h__ +#define __nv_gk208b_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gk208b_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk208b/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gk208b/nv_trim_hwref.h new file mode 100644 index 000000000..ae93a7b76 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk208b/nv_trim_hwref.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk208b_trim_hwref_h__ +#define __nv_gk208b_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gk208b_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_bus_hwref.h new file mode 100644 index 000000000..aa4de5758 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_bus_hwref_h__ +#define __nv_gk20a_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gk20a_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..ce2e1c34a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_ce2_pri_hwref_h__ +#define __nv_gk20a_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gk20a_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..100314dc6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_ctxsw_prog_addendum_hwref_h__ +#define __nv_gk20a_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gk20a_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..c8d1fb69b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_ctxsw_prog_hwref_h__ +#define __nv_gk20a_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 0:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_NUM_SMPC_QUADRANTS 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 5 + +#endif /* __nv_gk20a_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_fb_hwref.h new file mode 100644 index 000000000..ca5aec34d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_fb_hwref.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_fb_hwref_h__ +#define __nv_gk20a_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 +#define NV_PFB_PRI_MMU_DEBUG_CTRL 0x100cc4 +#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PFB_PRI_MMU_DEBUG_WR 0x100cc8 +#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE 1:0 +#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_DEBUG_WR_VOL 2:2 +#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR 31:4 +#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT 12 +#define NV_PFB_PRI_MMU_DEBUG_RD 0x100ccc +#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE 1:0 +#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_DEBUG_RD_VOL 2:2 +#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR 31:4 +#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT 12 +#define NV_PFB_PRI_MMU_VPR_INFO 0x100cd0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX 1:0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_LO 0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_HI 1 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_LO 2 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_HI 3 +#define NV_PFB_PRI_MMU_VPR_INFO_FETCH 2:2 + +#endif /* __nv_gk20a_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_fifo_hwref.h new file mode 100644 index 000000000..03a52cd56 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_fifo_hwref.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_fifo_hwref_h__ +#define __nv_gk20a_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x80 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x80 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_RUNLIST 19:16 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 1 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 1 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_RUNLIST_TIMESLICE(i) (0x2310+(i)*4) +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PFIFO_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 1 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 2 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 1 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gk20a_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_flush_hwref.h new file mode 100644 index 000000000..6d43be523 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_flush_hwref_h__ +#define __nv_gk20a_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gk20a_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..4b9244abc --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_graphics_nobundle_hwref.h @@ -0,0 +1,863 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_graphics_nobundle_hwref_h__ +#define __nv_gk20a_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_FE_GI 21:21 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x404194 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT 0x409008 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE 0x40900c +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK 0x409018 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST 0x40901c +#define NV_PGRAPH_PRI_FECS_FALCON_CURCTX 0x409050 +#define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX 0x409054 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1 0x409090 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 31:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD 0x409200 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC 3:0 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX 12:8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA 0x40920c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 8 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x100 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x62 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15 27:27 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15_EN 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_SMKEPLER_LP 12 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x240 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x648 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR 0x41a0ac +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB 5:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB 11:6 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_EXT 11:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_LOCKBOOST_SIZE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK 0x419ec8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT 11:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gk20a_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ltc_hwref.h new file mode 100644 index 000000000..a8cce6283 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ltc_hwref.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_ltc_hwref_h__ +#define __nv_gk20a_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140828 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e828 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gk20a_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_master_hwref.h new file mode 100644 index 000000000..654d974e8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_master_hwref.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_master_hwref_h__ +#define __nv_gk20a_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gk20a_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_mmu_hwref.h new file mode 100644 index 000000000..f2e85cc95 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_mmu_hwref_h__ +#define __nv_gk20a_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gk20a_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_pbdma_hwref.h new file mode 100644 index 000000000..c8b9de5e5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_pbdma_hwref.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_pbdma_hwref_h__ +#define __nv_gk20a_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 1 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_SYNCPOINTA(i) (0x400a4+(i)*0x2000) +#define NV_PPBDMA_SYNCPOINTA_PAYLOAD 31:0 +#define NV_PPBDMA_SYNCPOINTB(i) (0x400a8+(i)*0x2000) +#define NV_PPBDMA_SYNCPOINTB_OPERATION 1:0 +#define NV_PPBDMA_SYNCPOINTB_OPERATION_WAIT 0 +#define NV_PPBDMA_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NV_PPBDMA_SYNCPOINTB_WAIT_SWITCH_EN 1 +#define NV_PPBDMA_SYNCPOINTB_SYNCPT_INDEX 15:8 +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 1 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gk20a_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..da7ec342f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_pri_ringmaster_hwref_h__ +#define __nv_gk20a_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gk20a_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..8ef55b614 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_pri_ringstation_sys_hwref_h__ +#define __nv_gk20a_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gk20a_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_proj_hwref.h new file mode 100644 index 000000000..2192ba93d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_proj_hwref_h__ +#define __nv_gk20a_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 1 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 1 +#define NV_SCAL_LITTER_NUM_GPCS 1 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 1 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gk20a_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..a9e7a727b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_pwr_pri_hwref.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_pwr_pri_hwref_h__ +#define __nv_gk20a_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a480 +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a450+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 12 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gk20a_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ram_hwref.h new file mode 100644 index 000000000..540b472a5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_ram_hwref.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_ram_hwref_h__ +#define __nv_gk20a_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_SYNCPOINTA (0x29*32+31):(0x29*32+0) +#define NV_RAMFC_SYNCPOINTB (0x2a*32+31):(0x2a*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gk20a_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_therm_hwref.h new file mode 100644 index 000000000..9a727b2f8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_therm_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_therm_hwref_h__ +#define __nv_gk20a_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_EVT_EXT_THERM_0 0x20700 +#define NV_THERM_EVT_EXT_THERM_1 0x20704 +#define NV_THERM_EVT_EXT_THERM_2 0x20708 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gk20a_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_timer_hwref.h new file mode 100644 index 000000000..683d348b9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_timer_hwref_h__ +#define __nv_gk20a_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gk20a_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_top_hwref.h new file mode 100644 index 000000000..0a167f5e4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_top_hwref_h__ +#define __nv_gk20a_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gk20a_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..2d281ad64 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_trim_addendum_hwref_h__ +#define __nv_gk20a_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gk20a_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk20a/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gk20a/nv_trim_hwref.h new file mode 100644 index 000000000..838143ab5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk20a/nv_trim_hwref.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk20a_trim_hwref_h__ +#define __nv_gk20a_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_GPC_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gk20a_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_bus_hwref.h new file mode 100644 index 000000000..648465c67 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_bus_hwref_h__ +#define __nv_gm107_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gm107_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..11ba7739a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_ce2_pri_hwref_h__ +#define __nv_gm107_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gm107_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..5f77694cd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_ctxsw_prog_addendum_hwref_h__ +#define __nv_gm107_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gm107_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..069fda1d3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_ctxsw_prog_hwref.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_ctxsw_prog_hwref_h__ +#define __nv_gm107_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 2 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 0 + +#endif /* __nv_gm107_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_fb_hwref.h new file mode 100644 index 000000000..3923b634f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_fb_hwref.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_fb_hwref_h__ +#define __nv_gm107_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 +#define NV_PFB_PRI_MMU_VPR_INFO 0x100cd0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX 1:0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_LO 0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_HI 1 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_LO 2 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_HI 3 +#define NV_PFB_PRI_MMU_VPR_INFO_FETCH 2:2 + +#endif /* __nv_gm107_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_fifo_hwref.h new file mode 100644 index 000000000..e347afb73 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_fifo_hwref.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_fifo_hwref_h__ +#define __nv_gm107_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x800 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x800 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 5 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 5 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 13:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 2 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 2 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gm107_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_flush_hwref.h new file mode 100644 index 000000000..da3d356cd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_flush_hwref_h__ +#define __nv_gm107_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gm107_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_fuse_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_fuse_hwref.h new file mode 100644 index 000000000..8038f2f40 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_fuse_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_fuse_hwref_h__ +#define __nv_gm107_fuse_hwref_h__ + +#define NV_FUSE_CTRL_OPT_TPC_GPC(i) (0x21838+(i)*4) +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP 0x21944 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_DATA 1:0 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE 0x21948 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA 0:0 +#define NV_FUSE_STATUS_OPT_TPC_GPC(i) (0x21c38+(i)*4) +#define NV_FUSE_STATUS_OPT_FBP 0x21d38 +#define NV_FUSE_STATUS_OPT_FBP_IDX(i) (i):(i) +#define NV_FUSE_STATUS_OPT_FBIO 0x21c14 +#define NV_FUSE_STATUS_OPT_FBIO_DATA 15:0 + +#endif /* __nv_gm107_fuse_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..c4e57b96c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_graphics_nobundle_hwref.h @@ -0,0 +1,875 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_graphics_nobundle_hwref_h__ +#define __nv_gm107_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_FE_GI 21:21 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x404194 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT 0x409008 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE 0x40900c +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK 0x409018 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST 0x40901c +#define NV_PGRAPH_PRI_FECS_FALCON_CURCTX 0x409050 +#define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX 0x409054 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1 0x409090 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS 0x409130 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 31:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD 0x409200 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC 3:0 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX 12:8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA 0x40920c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 31:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x2c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x2c0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 31:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 15:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS_S1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S0 0x5046f0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S0 0x5046f4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S0 0x5046f8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S0 0x5046fc +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S1 0x504700 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S1 0x504704 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S1 0x504708 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S1 0x50470c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 19:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION 31:20 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_DEFAULT 0xaa0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_DEFAULT 0x1000 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_OFFSET 0x5030f4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_OFFSET 0x5030f8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR 0x41a0ac +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB 5:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB 11:6 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_EXT 11:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE 0x418e24 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE 0x418e28 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0x30 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL 0x418e30 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE(i) (0x418ea0+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3 31:16 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR 0x419c2c +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW 22:22 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE 31:31 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gm107_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_ltc_hwref.h new file mode 100644 index 000000000..20380647c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_ltc_hwref.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_ltc_hwref_h__ +#define __nv_gm107_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x14040c +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x14046c +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x140494 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x140518 +#define NV_PLTCG_LTC0_LTSS_INTR 0x14020c +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140214 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x1402a0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x1402a4 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142214 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x1422a0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x1422a4 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e20c +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e214 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e26c +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e270 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e274 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e278 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e280 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e2a0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e2a4 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e2ac +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e2b0 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17e318 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_VDC_4TO2_DISABLE 15:15 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17e338 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17e33c+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17e34c +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gm107_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_master_hwref.h new file mode 100644 index 000000000..10a883a63 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_master_hwref.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_master_hwref_h__ +#define __nv_gm107_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR(i) (0x100+(i)*4) +#define NV_PMC_INTR_PFIFO 8:8 +#define NV_PMC_INTR_PMU 24:24 +#define NV_PMC_INTR_LTC_ALL 25:25 +#define NV_PMC_INTR_PBUS 28:28 +#define NV_PMC_INTR_PRIV_RING 30:30 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gm107_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_mmu_hwref.h new file mode 100644 index 000000000..196454107 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_mmu_hwref_h__ +#define __nv_gm107_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gm107_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_pbdma_hwref.h new file mode 100644 index 000000000..4d913aa9b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_pbdma_hwref.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_pbdma_hwref_h__ +#define __nv_gm107_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 2 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE(i) (0x400f8+(i)*0x2000) +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PPBDMA_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 2 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gm107_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..61966c859 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_pri_ringmaster_hwref_h__ +#define __nv_gm107_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gm107_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..23f6bd6d0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_pri_ringstation_sys_hwref_h__ +#define __nv_gm107_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gm107_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_proj_hwref.h new file mode 100644 index 000000000..aff4d06fd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_proj_hwref_h__ +#define __nv_gm107_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x200 +#define NV_HOST_NUM_PBDMA 2 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 2 +#define NV_SCAL_LITTER_NUM_GPCS 1 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 3 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 5 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gm107_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..3bf08f9f0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_pwr_pri_hwref.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_pwr_pri_hwref_h__ +#define __nv_gm107_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_SCTL 0x10a240 +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_CPUCTL_ALIAS 0x10a130 +#define NV_PPWR_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a480 +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a450+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 12 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 +#define NV_PPWR_PMU_SCP_CTL_STAT 0x10ac08 +#define NV_PPWR_PMU_SCP_CTL_STAT_DEBUG_MODE 20:20 + +#endif /* __nv_gm107_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_ram_hwref.h new file mode 100644 index 000000000..2a499eaa1 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_ram_hwref.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_ram_hwref_h__ +#define __nv_gm107_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gm107_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_therm_hwref.h new file mode 100644 index 000000000..a0e8ce855 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_therm_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_therm_hwref_h__ +#define __nv_gm107_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gm107_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_timer_hwref.h new file mode 100644 index 000000000..b87e4995a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_timer_hwref_h__ +#define __nv_gm107_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gm107_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_top_hwref.h new file mode 100644 index 000000000..329acee85 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_top_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_top_hwref_h__ +#define __nv_gm107_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gm107_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..f904c6584 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_trim_addendum_hwref_h__ +#define __nv_gm107_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gm107_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm107/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gm107/nv_trim_hwref.h new file mode 100644 index 000000000..9f71df3cb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm107/nv_trim_hwref.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm107_trim_hwref_h__ +#define __nv_gm107_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN 7:0 +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW 15:8 +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_DVFS0 0x137010 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_COEFF 6:0 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX 14:8 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET 21:16 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_MODE 28:28 +#define NV_PTRIM_SYS_GPCPLL_DVFS1 0x137014 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_VCO_CTRL 8:0 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS0_MODE_DVFSPLL 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_DET 6:0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_STRB 7:7 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_CAL 14:8 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_SEL 15:15 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CTRL 27:16 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_SDM 28:28 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS 29:29 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS_CAL 30:30 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CAL_DONE 31:31 +#define NV_PTRIM_GPC_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gm107_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_bus_hwref.h new file mode 100644 index 000000000..e3e468daa --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_bus_hwref_h__ +#define __nv_gm108_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gm108_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..34bf4ddcb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_ce2_pri_hwref_h__ +#define __nv_gm108_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gm108_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..149c1d4a5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_ctxsw_prog_addendum_hwref_h__ +#define __nv_gm108_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gm108_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..149825fd6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_ctxsw_prog_hwref.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_ctxsw_prog_hwref_h__ +#define __nv_gm108_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 2 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 0 + +#endif /* __nv_gm108_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_fb_hwref.h new file mode 100644 index 000000000..57ee7e8d9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_fb_hwref.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_fb_hwref_h__ +#define __nv_gm108_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 +#define NV_PFB_PRI_MMU_VPR_INFO 0x100cd0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX 1:0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_LO 0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_HI 1 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_LO 2 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_HI 3 +#define NV_PFB_PRI_MMU_VPR_INFO_FETCH 2:2 + +#endif /* __nv_gm108_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_fifo_hwref.h new file mode 100644 index 000000000..7312fada6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_fifo_hwref.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_fifo_hwref_h__ +#define __nv_gm108_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x800 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x800 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 5 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 5 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 13:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 2 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 6 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 2 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gm108_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_flush_hwref.h new file mode 100644 index 000000000..94dea35ed --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_flush_hwref_h__ +#define __nv_gm108_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gm108_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_fuse_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_fuse_hwref.h new file mode 100644 index 000000000..f7d0fa699 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_fuse_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_fuse_hwref_h__ +#define __nv_gm108_fuse_hwref_h__ + +#define NV_FUSE_CTRL_OPT_TPC_GPC(i) (0x21838+(i)*4) +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP 0x21944 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_DATA 1:0 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE 0x21948 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA 0:0 +#define NV_FUSE_STATUS_OPT_TPC_GPC(i) (0x21c38+(i)*4) +#define NV_FUSE_STATUS_OPT_FBP 0x21d38 +#define NV_FUSE_STATUS_OPT_FBP_IDX(i) (i):(i) +#define NV_FUSE_STATUS_OPT_FBIO 0x21c14 +#define NV_FUSE_STATUS_OPT_FBIO_DATA 15:0 + +#endif /* __nv_gm108_fuse_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..cbcbd7699 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_graphics_nobundle_hwref.h @@ -0,0 +1,875 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_graphics_nobundle_hwref_h__ +#define __nv_gm108_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_FE_GI 21:21 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x404194 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT 0x409008 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE 0x40900c +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK 0x409018 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST 0x40901c +#define NV_PGRAPH_PRI_FECS_FALCON_CURCTX 0x409050 +#define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX 0x409054 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1 0x409090 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS 0x409130 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 31:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD 0x409200 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC 3:0 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX 12:8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA 0x40920c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 31:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x2c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x2c0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 31:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 15:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS_S1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S0 0x5046f0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S0 0x5046f4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S0 0x5046f8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S0 0x5046fc +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S1 0x504700 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S1 0x504704 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S1 0x504708 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S1 0x50470c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 19:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION 31:20 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_DEFAULT 0xaa0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_DEFAULT 0x1000 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_OFFSET 0x5030f4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_OFFSET 0x5030f8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR 0x41a0ac +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB 5:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB 11:6 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_EXT 11:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE 0x418e24 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE 0x418e28 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0x30 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL 0x418e30 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE(i) (0x418ea0+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3 31:16 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR 0x419c2c +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW 22:22 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE 31:31 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gm108_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_ltc_hwref.h new file mode 100644 index 000000000..9a3016ac2 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_ltc_hwref.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_ltc_hwref_h__ +#define __nv_gm108_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x14040c +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x14046c +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x140494 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x140518 +#define NV_PLTCG_LTC0_LTSS_INTR 0x14020c +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140214 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x1402a0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x1402a4 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142214 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x1422a0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x1422a4 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e20c +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e214 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e26c +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e270 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e274 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e278 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e280 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e2a0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e2a4 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e2ac +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e2b0 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17e318 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_VDC_4TO2_DISABLE 15:15 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17e338 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17e33c+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17e34c +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gm108_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_master_hwref.h new file mode 100644 index 000000000..18b506b90 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_master_hwref.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_master_hwref_h__ +#define __nv_gm108_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR(i) (0x100+(i)*4) +#define NV_PMC_INTR_PFIFO 8:8 +#define NV_PMC_INTR_PMU 24:24 +#define NV_PMC_INTR_LTC_ALL 25:25 +#define NV_PMC_INTR_PBUS 28:28 +#define NV_PMC_INTR_PRIV_RING 30:30 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gm108_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_mmu_hwref.h new file mode 100644 index 000000000..5dfe690b8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_mmu_hwref_h__ +#define __nv_gm108_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gm108_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_pbdma_hwref.h new file mode 100644 index 000000000..00a5f6637 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_pbdma_hwref.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_pbdma_hwref_h__ +#define __nv_gm108_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 2 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE(i) (0x400f8+(i)*0x2000) +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PPBDMA_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 2 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gm108_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..888d483c3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_pri_ringmaster_hwref.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_pri_ringmaster_hwref_h__ +#define __nv_gm108_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_ROP_L2 0x6c +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_ROP_L2_COUNT 4:0 + +#endif /* __nv_gm108_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..962814b2c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_pri_ringstation_sys_hwref_h__ +#define __nv_gm108_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gm108_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_proj_hwref.h new file mode 100644 index 000000000..87a3cb98f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_proj_hwref_h__ +#define __nv_gm108_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x200 +#define NV_HOST_NUM_PBDMA 2 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 2 +#define NV_SCAL_LITTER_NUM_GPCS 1 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 3 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 5 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gm108_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..f0bee53f0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_pwr_pri_hwref.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_pwr_pri_hwref_h__ +#define __nv_gm108_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_SCTL 0x10a240 +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_CPUCTL_ALIAS 0x10a130 +#define NV_PPWR_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a480 +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a450+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 12 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 +#define NV_PPWR_PMU_SCP_CTL_STAT 0x10ac08 +#define NV_PPWR_PMU_SCP_CTL_STAT_DEBUG_MODE 20:20 + +#endif /* __nv_gm108_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_ram_hwref.h new file mode 100644 index 000000000..a448b29d0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_ram_hwref.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_ram_hwref_h__ +#define __nv_gm108_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gm108_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_therm_hwref.h new file mode 100644 index 000000000..374caabf0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_therm_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_therm_hwref_h__ +#define __nv_gm108_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gm108_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_timer_hwref.h new file mode 100644 index 000000000..5971bad55 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_timer_hwref_h__ +#define __nv_gm108_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gm108_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_top_hwref.h new file mode 100644 index 000000000..517224a3d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_top_hwref.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_top_hwref_h__ +#define __nv_gm108_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gm108_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..9055f6d8e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_trim_addendum_hwref_h__ +#define __nv_gm108_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gm108_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm108/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gm108/nv_trim_hwref.h new file mode 100644 index 000000000..26a995ef9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm108/nv_trim_hwref.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm108_trim_hwref_h__ +#define __nv_gm108_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN 7:0 +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW 15:8 +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_DVFS0 0x137010 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_COEFF 6:0 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX 14:8 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET 21:16 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_MODE 28:28 +#define NV_PTRIM_SYS_GPCPLL_DVFS1 0x137014 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_VCO_CTRL 8:0 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS0_MODE_DVFSPLL 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_DET 6:0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_STRB 7:7 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_CAL 14:8 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_SEL 15:15 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CTRL 27:16 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_SDM 28:28 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS 29:29 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS_CAL 30:30 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CAL_DONE 31:31 +#define NV_PTRIM_GPC_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gm108_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_bus_hwref.h new file mode 100644 index 000000000..9bd3e534e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_bus_hwref_h__ +#define __nv_gm204_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gm204_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..ce0f7f641 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_ce2_pri_hwref_h__ +#define __nv_gm204_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gm204_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..c1ff9c00e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_ctxsw_prog_addendum_hwref_h__ +#define __nv_gm204_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gm204_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..517017cbb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_ctxsw_prog_hwref_h__ +#define __nv_gm204_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PC_SAMPLING 6:6 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 2 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 0 + +#endif /* __nv_gm204_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_fb_hwref.h new file mode 100644 index 000000000..ee1f9c637 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_fb_hwref.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_fb_hwref_h__ +#define __nv_gm204_fb_hwref_h__ + +#define NV_PFB_FBHUB_NUM_ACTIVE_LTCS 0x100800 +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 +#define NV_PFB_PRI_MMU_DEBUG_CTRL 0x100cc4 +#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PFB_PRI_MMU_DEBUG_WR 0x100cc8 +#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE 1:0 +#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_DEBUG_WR_VOL 2:2 +#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR 31:4 +#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT 12 +#define NV_PFB_PRI_MMU_DEBUG_RD 0x100ccc +#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE 1:0 +#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_DEBUG_RD_VOL 2:2 +#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR 31:4 +#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT 12 +#define NV_PFB_PRI_MMU_VPR_INFO 0x100cd0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX 1:0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_LO 0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_HI 1 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_LO 2 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_HI 3 +#define NV_PFB_PRI_MMU_VPR_INFO_FETCH 2:2 +#define NV_PFB_PRI_MMU_WPR_INFO 0x100cd4 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX 3:0 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_ALLOW_READ 0 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_ALLOW_WRITE 1 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR1_ADDR_LO 2 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR1_ADDR_HI 3 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR2_ADDR_LO 4 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR2_ADDR_HI 5 +#define NV_PFB_PRI_MMU_PHYS_SECURE 0x100ce4 + +#endif /* __nv_gm204_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_fifo_hwref.h new file mode 100644 index 000000000..6e22a1f2a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_fifo_hwref.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_fifo_hwref_h__ +#define __nv_gm204_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 13:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 3 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 8 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 3 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gm204_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_flush_hwref.h new file mode 100644 index 000000000..3c9ed863e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_flush_hwref_h__ +#define __nv_gm204_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gm204_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_fuse_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_fuse_hwref.h new file mode 100644 index 000000000..00690d033 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_fuse_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_fuse_hwref_h__ +#define __nv_gm204_fuse_hwref_h__ + +#define NV_FUSE_CTRL_OPT_TPC_GPC(i) (0x21838+(i)*4) +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP 0x21944 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_DATA 1:0 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE 0x21948 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA 0:0 +#define NV_FUSE_STATUS_OPT_TPC_GPC(i) (0x21c38+(i)*4) +#define NV_FUSE_STATUS_OPT_ROP_L2_FBP(i) (0x21d70+(i)*4) +#define NV_FUSE_STATUS_OPT_FBP 0x21d38 +#define NV_FUSE_STATUS_OPT_FBP_IDX(i) (i):(i) +#define NV_FUSE_STATUS_OPT_FBIO 0x21c14 +#define NV_FUSE_STATUS_OPT_FBIO_DATA 15:0 + +#endif /* __nv_gm204_fuse_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..fc3ff213e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_graphics_nobundle_hwref.h @@ -0,0 +1,875 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_graphics_nobundle_hwref_h__ +#define __nv_gm204_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_FE_GI 21:21 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x404194 +#define NV_PGRAPH_PRI_FE_TPC_FS 0x4041c4 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT 0x409008 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE 0x40900c +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK 0x409018 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST 0x40901c +#define NV_PGRAPH_PRI_FECS_FALCON_CURCTX 0x409050 +#define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX 0x409054 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1 0x409090 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS 0x409130 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 31:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD 0x409200 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC 3:0 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX 12:8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA 0x40920c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 31:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x780 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x780 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 31:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 15:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2 0x405848 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2 0x40584c +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH24_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH24_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID(i) (0x405b60+((i)*4)) +#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC0 3:0 +#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC1 11:8 +#define NV_PGRAPH_PRI_CWD_SM_ID(i) (0x405ba0+((i)*4)) +#define NV_PGRAPH_PRI_CWD_SM_ID_TPC0 7:0 +#define NV_PGRAPH_PRI_CWD_SM_ID_TPC1 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS_S1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S0 0x5046f0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S0 0x5046f4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S0 0x5046f8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S0 0x5046fc +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S1 0x504700 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S1 0x504704 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S1 0x504708 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S1 0x50470c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 19:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION 31:20 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_DEFAULT 0x400 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_DEFAULT 0x1000 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_OFFSET 0x5030f4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_OFFSET 0x5030f8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR 0x41a0ac +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB 5:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB 11:6 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_EXT 11:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE 0x418e24 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE 0x418e28 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0x30 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL 0x418e30 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE(i) (0x418ea0+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3 31:16 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS 0x4188ac +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR 0x419c2c +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW 22:22 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_LTCS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE 31:31 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_LTCS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gm204_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_ltc_hwref.h new file mode 100644 index 000000000..7875d5b41 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_ltc_hwref.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_ltc_hwref_h__ +#define __nv_gm204_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x14040c +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x14046c +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x140494 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x140518 +#define NV_PLTCG_LTC0_LTSS_INTR 0x14020c +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140214 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x1402a0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x1402a4 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142214 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x1422a0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x1422a4 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_MISC_LTC_NUM_ACTIVE_LTCS 0x17e000 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e20c +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS 30:30 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e214 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e26c +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e270 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e274 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e278 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS 0x17e27c +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e280 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e2a0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e2a4 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e2ac +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e2b0 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17e318 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_VDC_4TO2_DISABLE 15:15 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17e338 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17e33c+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17e34c +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gm204_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_master_hwref.h new file mode 100644 index 000000000..10be66fbd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_master_hwref.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_master_hwref_h__ +#define __nv_gm204_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR(i) (0x100+(i)*4) +#define NV_PMC_INTR_PFIFO 8:8 +#define NV_PMC_INTR_PMU 24:24 +#define NV_PMC_INTR_LTC_ALL 25:25 +#define NV_PMC_INTR_PBUS 28:28 +#define NV_PMC_INTR_PRIV_RING 30:30 +#define NV_PMC_INTR_PGRAPH 12:12 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gm204_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_mmu_hwref.h new file mode 100644 index 000000000..78b217aad --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_mmu_hwref.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_mmu_hwref_h__ +#define __nv_gm204_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_S8 0x2a +#define NV_MMU_PTE_KIND_S8_2S 0x2b +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gm204_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_pbdma_hwref.h new file mode 100644 index 000000000..08cb4de72 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_pbdma_hwref.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_pbdma_hwref_h__ +#define __nv_gm204_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE(i) (0x400f8+(i)*0x2000) +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PPBDMA_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gm204_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..0820234b6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_pri_ringmaster_hwref.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_pri_ringmaster_hwref_h__ +#define __nv_gm204_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_ROP_L2 0x12006c +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_ROP_L2_COUNT 4:0 + +#endif /* __nv_gm204_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..fbbf5bfad --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_pri_ringstation_sys_hwref_h__ +#define __nv_gm204_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gm204_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_proj_hwref.h new file mode 100644 index 000000000..e5d6adca3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_proj_hwref_h__ +#define __nv_gm204_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x200 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 6 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 4 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gm204_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..0d0a41c50 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_pwr_pri_hwref.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_pwr_pri_hwref_h__ +#define __nv_gm204_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_SCTL 0x10a240 +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_CPUCTL_ALIAS_EN 6:6 +#define NV_PPWR_FALCON_CPUCTL_ALIAS 0x10a130 +#define NV_PPWR_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a480 +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a450+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 12 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10ae00+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 +#define NV_PPWR_PMU_SCP_CTL_STAT 0x10ac08 +#define NV_PPWR_PMU_SCP_CTL_STAT_DEBUG_MODE 20:20 + +#endif /* __nv_gm204_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_ram_hwref.h new file mode 100644 index 000000000..513e32003 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_ram_hwref.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_ram_hwref_h__ +#define __nv_gm204_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_BIG_PAGE_SIZE (0x80*32+11):(0x80*32+11) +#define NV_RAMIN_BIG_PAGE_SIZE_128KB 0 +#define NV_RAMIN_BIG_PAGE_SIZE_64KB 1 +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gm204_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_therm_hwref.h new file mode 100644 index 000000000..3e636d246 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_therm_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_therm_hwref_h__ +#define __nv_gm204_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gm204_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_timer_hwref.h new file mode 100644 index 000000000..9fd5cb4be --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_timer_hwref_h__ +#define __nv_gm204_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gm204_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_top_hwref.h new file mode 100644 index 000000000..c8b247e4a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_top_hwref_h__ +#define __nv_gm204_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_LTC_PER_FBP 0x22450 +#define NV_PTOP_SCAL_NUM_LTC_PER_FBP_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_LTCS 0x22454 +#define NV_PTOP_SCAL_NUM_SLICES_PER_LTC 0x2245c +#define NV_PTOP_SCAL_NUM_SLICES_PER_LTC_VALUE 4:0 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gm204_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..3fdb3aefd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_trim_addendum_hwref_h__ +#define __nv_gm204_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gm204_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm204/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gm204/nv_trim_hwref.h new file mode 100644 index 000000000..8a78e603a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm204/nv_trim_hwref.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm204_trim_hwref_h__ +#define __nv_gm204_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN 7:0 +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW 15:8 +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_DVFS0 0x137010 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_COEFF 6:0 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX 14:8 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET 21:16 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_MODE 28:28 +#define NV_PTRIM_SYS_GPCPLL_DVFS1 0x137014 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_VCO_CTRL 8:0 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_CFG3_DFS_TESTOUT 30:24 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS0_MODE_DVFSPLL 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_DET 6:0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_STRB 7:7 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_CAL 14:8 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_SEL 15:15 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CTRL 27:16 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_SDM 28:28 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS 29:29 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS_CAL 30:30 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CAL_DONE 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG_GPCPLL_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gm204_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_bus_hwref.h new file mode 100644 index 000000000..b35f2b872 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_bus_hwref_h__ +#define __nv_gm206_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gm206_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..911b81d52 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_ce2_pri_hwref_h__ +#define __nv_gm206_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gm206_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..e3d3386c3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_ctxsw_prog_addendum_hwref_h__ +#define __nv_gm206_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gm206_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..736833e23 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_ctxsw_prog_hwref_h__ +#define __nv_gm206_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PC_SAMPLING 6:6 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 2 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 0 + +#endif /* __nv_gm206_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_fb_hwref.h new file mode 100644 index 000000000..37dd7f754 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_fb_hwref.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_fb_hwref_h__ +#define __nv_gm206_fb_hwref_h__ + +#define NV_PFB_FBHUB_NUM_ACTIVE_LTCS 0x100800 +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 +#define NV_PFB_PRI_MMU_DEBUG_CTRL 0x100cc4 +#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PFB_PRI_MMU_DEBUG_WR 0x100cc8 +#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE 1:0 +#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_DEBUG_WR_VOL 2:2 +#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR 31:4 +#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT 12 +#define NV_PFB_PRI_MMU_DEBUG_RD 0x100ccc +#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE 1:0 +#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_DEBUG_RD_VOL 2:2 +#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR 31:4 +#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT 12 +#define NV_PFB_PRI_MMU_VPR_INFO 0x100cd0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX 1:0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_LO 0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_HI 1 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_LO 2 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_HI 3 +#define NV_PFB_PRI_MMU_VPR_INFO_FETCH 2:2 +#define NV_PFB_PRI_MMU_WPR_INFO 0x100cd4 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX 3:0 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_ALLOW_READ 0 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_ALLOW_WRITE 1 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR1_ADDR_LO 2 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR1_ADDR_HI 3 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR2_ADDR_LO 4 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR2_ADDR_HI 5 +#define NV_PFB_PRI_MMU_PHYS_SECURE 0x100ce4 + +#endif /* __nv_gm206_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_fifo_hwref.h new file mode 100644 index 000000000..1b48b7018 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_fifo_hwref.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_fifo_hwref_h__ +#define __nv_gm206_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 13:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 3 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 8 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 3 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gm206_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_flush_hwref.h new file mode 100644 index 000000000..752629026 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_flush_hwref_h__ +#define __nv_gm206_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gm206_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_fuse_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_fuse_hwref.h new file mode 100644 index 000000000..feae73709 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_fuse_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_fuse_hwref_h__ +#define __nv_gm206_fuse_hwref_h__ + +#define NV_FUSE_CTRL_OPT_TPC_GPC(i) (0x21838+(i)*4) +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP 0x21944 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_DATA 1:0 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE 0x21948 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA 0:0 +#define NV_FUSE_STATUS_OPT_TPC_GPC(i) (0x21c38+(i)*4) +#define NV_FUSE_STATUS_OPT_ROP_L2_FBP(i) (0x21d70+(i)*4) +#define NV_FUSE_STATUS_OPT_FBP 0x21d38 +#define NV_FUSE_STATUS_OPT_FBP_IDX(i) (i):(i) +#define NV_FUSE_STATUS_OPT_FBIO 0x21c14 +#define NV_FUSE_STATUS_OPT_FBIO_DATA 15:0 + +#endif /* __nv_gm206_fuse_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..9c905bd2f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_graphics_nobundle_hwref.h @@ -0,0 +1,875 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_graphics_nobundle_hwref_h__ +#define __nv_gm206_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_FE_GI 21:21 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x404194 +#define NV_PGRAPH_PRI_FE_TPC_FS 0x4041c4 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT 0x409008 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE 0x40900c +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK 0x409018 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST 0x40901c +#define NV_PGRAPH_PRI_FECS_FALCON_CURCTX 0x409050 +#define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX 0x409054 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1 0x409090 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS 0x409130 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 31:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD 0x409200 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC 3:0 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX 12:8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA 0x40920c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 31:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x780 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x780 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 31:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 15:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2 0x405848 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2 0x40584c +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH24_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH24_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID(i) (0x405b60+((i)*4)) +#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC0 3:0 +#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC1 11:8 +#define NV_PGRAPH_PRI_CWD_SM_ID(i) (0x405ba0+((i)*4)) +#define NV_PGRAPH_PRI_CWD_SM_ID_TPC0 7:0 +#define NV_PGRAPH_PRI_CWD_SM_ID_TPC1 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS_S1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S0 0x5046f0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S0 0x5046f4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S0 0x5046f8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S0 0x5046fc +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S1 0x504700 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S1 0x504704 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S1 0x504708 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S1 0x50470c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 19:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION 31:20 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_DEFAULT 0x400 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_DEFAULT 0x1000 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_OFFSET 0x5030f4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_OFFSET 0x5030f8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR 0x41a0ac +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB 5:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB 11:6 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_EXT 11:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE 0x418e24 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE 0x418e28 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0x30 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL 0x418e30 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE(i) (0x418ea0+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3 31:16 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS 0x4188ac +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR 0x419c2c +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW 22:22 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_LTCS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE 31:31 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_LTCS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gm206_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_ltc_hwref.h new file mode 100644 index 000000000..3cc03824a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_ltc_hwref.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_ltc_hwref_h__ +#define __nv_gm206_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x14040c +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x14046c +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x140494 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x140518 +#define NV_PLTCG_LTC0_LTSS_INTR 0x14020c +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140214 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x1402a0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x1402a4 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142214 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x1422a0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x1422a4 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_MISC_LTC_NUM_ACTIVE_LTCS 0x17e000 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e20c +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS 30:30 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e214 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e26c +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e270 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e274 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e278 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS 0x17e27c +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e280 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e2a0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e2a4 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e2ac +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e2b0 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17e318 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_VDC_4TO2_DISABLE 15:15 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17e338 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17e33c+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17e34c +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gm206_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_master_hwref.h new file mode 100644 index 000000000..b130759f3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_master_hwref.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_master_hwref_h__ +#define __nv_gm206_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR(i) (0x100+(i)*4) +#define NV_PMC_INTR_PFIFO 8:8 +#define NV_PMC_INTR_PMU 24:24 +#define NV_PMC_INTR_LTC_ALL 25:25 +#define NV_PMC_INTR_PBUS 28:28 +#define NV_PMC_INTR_PRIV_RING 30:30 +#define NV_PMC_INTR_PGRAPH 12:12 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gm206_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_mmu_hwref.h new file mode 100644 index 000000000..cbe615ea2 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_mmu_hwref.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_mmu_hwref_h__ +#define __nv_gm206_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_S8 0x2a +#define NV_MMU_PTE_KIND_S8_2S 0x2b +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gm206_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_pbdma_hwref.h new file mode 100644 index 000000000..54db3882b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_pbdma_hwref.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_pbdma_hwref_h__ +#define __nv_gm206_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE(i) (0x400f8+(i)*0x2000) +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PPBDMA_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gm206_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..3a084067e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_pri_ringmaster_hwref.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_pri_ringmaster_hwref_h__ +#define __nv_gm206_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_ROP_L2 0x12006c +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_ROP_L2_COUNT 4:0 + +#endif /* __nv_gm206_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..f65fccde1 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_pri_ringstation_sys_hwref_h__ +#define __nv_gm206_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gm206_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_proj_hwref.h new file mode 100644 index 000000000..5369b70c8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_proj_hwref_h__ +#define __nv_gm206_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x200 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 6 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 4 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gm206_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..75dd9bdd6 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_pwr_pri_hwref.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_pwr_pri_hwref_h__ +#define __nv_gm206_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_SCTL 0x10a240 +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_CPUCTL_ALIAS_EN 6:6 +#define NV_PPWR_FALCON_CPUCTL_ALIAS 0x10a130 +#define NV_PPWR_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a480 +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a450+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 12 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10ae00+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 +#define NV_PPWR_PMU_SCP_CTL_STAT 0x10ac08 +#define NV_PPWR_PMU_SCP_CTL_STAT_DEBUG_MODE 20:20 + +#endif /* __nv_gm206_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_ram_hwref.h new file mode 100644 index 000000000..3dbf0ca88 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_ram_hwref.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_ram_hwref_h__ +#define __nv_gm206_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_BIG_PAGE_SIZE (0x80*32+11):(0x80*32+11) +#define NV_RAMIN_BIG_PAGE_SIZE_128KB 0 +#define NV_RAMIN_BIG_PAGE_SIZE_64KB 1 +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gm206_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_therm_hwref.h new file mode 100644 index 000000000..7ee3187b9 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_therm_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_therm_hwref_h__ +#define __nv_gm206_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gm206_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_timer_hwref.h new file mode 100644 index 000000000..f8e2ea71f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_timer_hwref_h__ +#define __nv_gm206_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gm206_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_top_hwref.h new file mode 100644 index 000000000..f00018b54 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_top_hwref_h__ +#define __nv_gm206_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_LTC_PER_FBP 0x22450 +#define NV_PTOP_SCAL_NUM_LTC_PER_FBP_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_LTCS 0x22454 +#define NV_PTOP_SCAL_NUM_SLICES_PER_LTC 0x2245c +#define NV_PTOP_SCAL_NUM_SLICES_PER_LTC_VALUE 4:0 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gm206_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..e8f8a363f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_trim_addendum_hwref_h__ +#define __nv_gm206_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gm206_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm206/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gm206/nv_trim_hwref.h new file mode 100644 index 000000000..a786e2c29 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm206/nv_trim_hwref.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm206_trim_hwref_h__ +#define __nv_gm206_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN 7:0 +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW 15:8 +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_DVFS0 0x137010 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_COEFF 6:0 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX 14:8 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET 21:16 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_MODE 28:28 +#define NV_PTRIM_SYS_GPCPLL_DVFS1 0x137014 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_VCO_CTRL 8:0 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_CFG3_DFS_TESTOUT 30:24 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS0_MODE_DVFSPLL 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_DET 6:0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_STRB 7:7 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_CAL 14:8 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_SEL 15:15 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CTRL 27:16 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_SDM 28:28 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS 29:29 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS_CAL 30:30 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CAL_DONE 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG_GPCPLL_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gm206_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_bus_hwref.h new file mode 100644 index 000000000..a0fb26c52 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_bus_hwref_h__ +#define __nv_gm20b_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gm20b_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..05ebc0e04 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_ce2_pri_hwref_h__ +#define __nv_gm20b_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gm20b_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..56a2d8db2 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_ctxsw_prog_addendum_hwref_h__ +#define __nv_gm20b_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gm20b_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..2f3a873c1 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_ctxsw_prog_hwref_h__ +#define __nv_gm20b_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PC_SAMPLING 6:6 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 2 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 0 + +#endif /* __nv_gm20b_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_fb_hwref.h new file mode 100644 index 000000000..ffaf7c7ee --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_fb_hwref.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_fb_hwref_h__ +#define __nv_gm20b_fb_hwref_h__ + +#define NV_PFB_FBHUB_NUM_ACTIVE_LTCS 0x100800 +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 +#define NV_PFB_PRI_MMU_DEBUG_CTRL 0x100cc4 +#define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PFB_PRI_MMU_DEBUG_WR 0x100cc8 +#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE 1:0 +#define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_DEBUG_WR_VOL 2:2 +#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR 31:4 +#define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT 12 +#define NV_PFB_PRI_MMU_DEBUG_RD 0x100ccc +#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE 1:0 +#define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_DEBUG_RD_VOL 2:2 +#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR 31:4 +#define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT 12 +#define NV_PFB_PRI_MMU_VPR_INFO 0x100cd0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX 1:0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_LO 0 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_ADDR_HI 1 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_LO 2 +#define NV_PFB_PRI_MMU_VPR_INFO_INDEX_CYA_HI 3 +#define NV_PFB_PRI_MMU_VPR_INFO_FETCH 2:2 +#define NV_PFB_PRI_MMU_WPR_INFO 0x100cd4 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX 3:0 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_ALLOW_READ 0 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_ALLOW_WRITE 1 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR1_ADDR_LO 2 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR1_ADDR_HI 3 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR2_ADDR_LO 4 +#define NV_PFB_PRI_MMU_WPR_INFO_INDEX_WPR2_ADDR_HI 5 +#define NV_PFB_PRI_MMU_PHYS_SECURE 0x100ce4 + +#endif /* __nv_gm20b_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_fifo_hwref.h new file mode 100644 index 000000000..b2f6ee2f1 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_fifo_hwref.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_fifo_hwref_h__ +#define __nv_gm20b_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x200 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x200 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 1 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 1 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 13:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 1 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 2 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 1 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gm20b_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_flush_hwref.h new file mode 100644 index 000000000..472089490 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_flush_hwref_h__ +#define __nv_gm20b_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gm20b_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_fuse_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_fuse_hwref.h new file mode 100644 index 000000000..252246298 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_fuse_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_fuse_hwref_h__ +#define __nv_gm20b_fuse_hwref_h__ + +#define NV_FUSE_CTRL_OPT_TPC_GPC(i) (0x21838+(i)*4) +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP 0x21944 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_DATA 1:0 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE 0x21948 +#define NV_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA 0:0 +#define NV_FUSE_STATUS_OPT_TPC_GPC(i) (0x21c38+(i)*4) +#define NV_FUSE_STATUS_OPT_ROP_L2_FBP(i) (0x21d70+(i)*4) +#define NV_FUSE_STATUS_OPT_FBP 0x21d38 +#define NV_FUSE_STATUS_OPT_FBP_IDX(i) (i):(i) +#define NV_FUSE_STATUS_OPT_FBIO 0x21c14 +#define NV_FUSE_STATUS_OPT_FBIO_DATA 15:0 + +#endif /* __nv_gm20b_fuse_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..eff5b4457 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_graphics_nobundle_hwref.h @@ -0,0 +1,875 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_graphics_nobundle_hwref_h__ +#define __nv_gm20b_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_FE_GI 21:21 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x404194 +#define NV_PGRAPH_PRI_FE_TPC_FS 0x4041c4 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQSTAT 0x409008 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMODE 0x40900c +#define NV_PGRAPH_PRI_FECS_FALCON_IRQMASK 0x409018 +#define NV_PGRAPH_PRI_FECS_FALCON_IRQDEST 0x40901c +#define NV_PGRAPH_PRI_FECS_FALCON_CURCTX 0x409050 +#define NV_PGRAPH_PRI_FECS_FALCON_NXTCTX 0x409054 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUG1 0x409090 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS 0x409130 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 31:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD 0x409200 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC 3:0 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_CMD_IDX 12:8 +#define NV_PGRAPH_PRI_FECS_FALCON_ICD_RDATA 0x40920c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 31:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x1c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x182 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 31:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 15:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2 0x405848 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_2_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2 0x40584c +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH24_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_2_SPH24_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 24 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID(i) (0x405b60+((i)*4)) +#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC0 3:0 +#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC1 11:8 +#define NV_PGRAPH_PRI_CWD_SM_ID(i) (0x405ba0+((i)*4)) +#define NV_PGRAPH_PRI_CWD_SM_ID_TPC0 7:0 +#define NV_PGRAPH_PRI_CWD_SM_ID_TPC1 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS_S1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S0 0x5046f0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S0 0x5046f4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S0 0x5046f8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S0 0x5046fc +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S1 0x504700 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S1 0x504704 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S1 0x504708 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S1 0x50470c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 19:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SM_VERSION 31:20 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_DEFAULT 0x400 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_DEFAULT 0x800 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_BETA_CB_OFFSET 0x5030f4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_ALPHA_CB_OFFSET 0x5030f8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR 0x41a0ac +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB 5:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_LSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB 11:6 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_MSB_INIT 0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_ADDR_EXT 11:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE 0x418e24 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE 0x418e28 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 24 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL 0x418e30 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE(i) (0x418ea0+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_V 15:0 +#define NV_PGRAPH_PRI_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3 31:16 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS 0x4188ac +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR 0x419c2c +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW 22:22 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT 23:23 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_LTCS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE 31:31 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_LTCS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gm20b_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ltc_hwref.h new file mode 100644 index 000000000..b37fb5baf --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ltc_hwref.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_ltc_hwref_h__ +#define __nv_gm20b_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x14040c +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x14046c +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x140494 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x140518 +#define NV_PLTCG_LTC0_LTSS_INTR 0x14020c +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140214 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x1402a0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x1402a4 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142214 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x1422a0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x1422a4 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_MISC_LTC_NUM_ACTIVE_LTCS 0x17e000 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e20c +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS 30:30 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e214 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e26c +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e270 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e274 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e278 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS 0x17e27c +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e280 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e2a0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e2a4 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e2ac +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e2b0 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17e318 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_VDC_4TO2_DISABLE 15:15 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17e338 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17e33c+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17e34c +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gm20b_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_master_hwref.h new file mode 100644 index 000000000..7c5d32850 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_master_hwref.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_master_hwref_h__ +#define __nv_gm20b_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR(i) (0x100+(i)*4) +#define NV_PMC_INTR_PFIFO 8:8 +#define NV_PMC_INTR_PMU 24:24 +#define NV_PMC_INTR_LTC_ALL 25:25 +#define NV_PMC_INTR_PBUS 28:28 +#define NV_PMC_INTR_PRIV_RING 30:30 +#define NV_PMC_INTR_PGRAPH 12:12 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gm20b_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_mmu_hwref.h new file mode 100644 index 000000000..ca64b3b9b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_mmu_hwref.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_mmu_hwref_h__ +#define __nv_gm20b_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_S8 0x2a +#define NV_MMU_PTE_KIND_S8_2S 0x2b +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gm20b_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_pbdma_hwref.h new file mode 100644 index 000000000..1f37a3799 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_pbdma_hwref.h @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_pbdma_hwref_h__ +#define __nv_gm20b_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 1 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_SYNCPOINTA(i) (0x400a4+(i)*0x2000) +#define NV_PPBDMA_SYNCPOINTA_PAYLOAD 31:0 +#define NV_PPBDMA_SYNCPOINTB(i) (0x400a8+(i)*0x2000) +#define NV_PPBDMA_SYNCPOINTB_OPERATION 1:0 +#define NV_PPBDMA_SYNCPOINTB_OPERATION_WAIT 0 +#define NV_PPBDMA_SYNCPOINTB_WAIT_SWITCH 4:4 +#define NV_PPBDMA_SYNCPOINTB_WAIT_SWITCH_EN 1 +#define NV_PPBDMA_SYNCPOINTB_SYNCPT_INDEX 15:8 +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE(i) (0x400f8+(i)*0x2000) +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PPBDMA_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PPBDMA_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 1 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gm20b_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..fc37a2f43 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_pri_ringmaster_hwref.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_pri_ringmaster_hwref_h__ +#define __nv_gm20b_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_ROP_L2 0x12006c +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_ROP_L2_COUNT 4:0 + +#endif /* __nv_gm20b_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..9dd2f8c44 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_pri_ringstation_sys_hwref_h__ +#define __nv_gm20b_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gm20b_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_proj_hwref.h new file mode 100644 index 000000000..0ba9f96de --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_proj_hwref_h__ +#define __nv_gm20b_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x200 +#define NV_HOST_NUM_PBDMA 1 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 1 +#define NV_SCAL_LITTER_NUM_GPCS 1 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 1 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gm20b_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..a3fe9e717 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_pwr_pri_hwref.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_pwr_pri_hwref_h__ +#define __nv_gm20b_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_SCTL 0x10a240 +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_CPUCTL_ALIAS_EN 6:6 +#define NV_PPWR_FALCON_CPUCTL_ALIAS 0x10a130 +#define NV_PPWR_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a480 +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a450+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 12 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10ae00+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 +#define NV_PPWR_PMU_SCP_CTL_STAT 0x10ac08 +#define NV_PPWR_PMU_SCP_CTL_STAT_DEBUG_MODE 20:20 + +#endif /* __nv_gm20b_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ram_hwref.h new file mode 100644 index 000000000..e93339d6a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_ram_hwref.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_ram_hwref_h__ +#define __nv_gm20b_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_BIG_PAGE_SIZE (0x80*32+11):(0x80*32+11) +#define NV_RAMIN_BIG_PAGE_SIZE_128KB 0 +#define NV_RAMIN_BIG_PAGE_SIZE_64KB 1 +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_SYNCPOINTA (0x29*32+31):(0x29*32+0) +#define NV_RAMFC_SYNCPOINTB (0x2a*32+31):(0x2a*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gm20b_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_therm_hwref.h new file mode 100644 index 000000000..bdeea2e95 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_therm_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_therm_hwref_h__ +#define __nv_gm20b_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_EVT_EXT_THERM_0 0x20700 +#define NV_THERM_EVT_EXT_THERM_1 0x20704 +#define NV_THERM_EVT_EXT_THERM_2 0x20708 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gm20b_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_timer_hwref.h new file mode 100644 index 000000000..93ab05c0d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_timer_hwref_h__ +#define __nv_gm20b_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gm20b_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_top_hwref.h new file mode 100644 index 000000000..f4f83ccc0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_top_hwref_h__ +#define __nv_gm20b_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_LTC_PER_FBP 0x22450 +#define NV_PTOP_SCAL_NUM_LTC_PER_FBP_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_LTCS 0x22454 +#define NV_PTOP_SCAL_NUM_SLICES_PER_LTC 0x2245c +#define NV_PTOP_SCAL_NUM_SLICES_PER_LTC_VALUE 4:0 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gm20b_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..d7522e3fe --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_trim_addendum_hwref_h__ +#define __nv_gm20b_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gm20b_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gm20b/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gm20b/nv_trim_hwref.h new file mode 100644 index 000000000..0bb2c8e5c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gm20b/nv_trim_hwref.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gm20b_trim_hwref_h__ +#define __nv_gm20b_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN 7:0 +#define NV_PTRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW 15:8 +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_DVFS0 0x137010 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_COEFF 6:0 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX 14:8 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET 21:16 +#define NV_PTRIM_SYS_GPCPLL_DVFS0_MODE 28:28 +#define NV_PTRIM_SYS_GPCPLL_DVFS1 0x137014 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_VCO_CTRL 8:0 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_CFG3_DFS_TESTOUT 30:24 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_GPCPLL_DVFS2 0x137020 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS0_MODE_DVFSPLL 0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_DET 6:0 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_STRB 7:7 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_CAL 14:8 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_EXT_SEL 15:15 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CTRL 27:16 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_SDM 28:28 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS 29:29 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_EN_DFS_CAL 30:30 +#define NV_PTRIM_GPC_GPCPLL_DVFS1_DFS_CAL_DONE 31:31 +#define NV_PTRIM_GPC_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_GPCPLL_DVFS2 0x132820 +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG_GPCPLL_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gm20b_trim_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_bus_hwref.h new file mode 100644 index 000000000..cf346fbbd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_bus_hwref_h__ +#define __nv_gt215_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_gt215_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_fifo_hwref.h new file mode 100644 index 000000000..d0e29d9a4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_fifo_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_fifo_hwref_h__ +#define __nv_gt215_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_1 0x2144 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_gt215_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_flush_hwref.h new file mode 100644 index 000000000..ac4b3b83a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_flush_hwref_h__ +#define __nv_gt215_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gt215_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..1946e6bd2 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_graphics_nobundle_hwref_h__ +#define __nv_gt215_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_gt215_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_master_hwref.h new file mode 100644 index 000000000..90606b1f5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_master_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_master_hwref_h__ +#define __nv_gt215_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 18:18 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 18:18 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_CE0 13:13 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_gt215_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_mmu_hwref.h new file mode 100644 index 000000000..59d3c903e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_mmu_hwref.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_mmu_hwref_h__ +#define __nv_gt215_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+29):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 +#define NV_MMU_PTE_KIND_Z16 0x68 +#define NV_MMU_PTE_KIND_X8C24 0x44 + +#endif /* __nv_gt215_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..9566381d1 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_pwr_pri_hwref.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_pwr_pri_hwref_h__ +#define __nv_gt215_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 8 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 3:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 + +#endif /* __nv_gt215_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_ram_hwref.h new file mode 100644 index 000000000..c2ac71ab0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_ram_hwref_h__ +#define __nv_gt215_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_gt215_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_therm_hwref.h new file mode 100644 index 000000000..a21697fad --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_therm_hwref_h__ +#define __nv_gt215_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_gt215_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt215/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gt215/nv_timer_hwref.h new file mode 100644 index 000000000..97cad054b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt215/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt215_timer_hwref_h__ +#define __nv_gt215_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gt215_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_bus_hwref.h new file mode 100644 index 000000000..4bb48560d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_bus_hwref_h__ +#define __nv_gt216_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_gt216_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_fifo_hwref.h new file mode 100644 index 000000000..9df45ec01 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_fifo_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_fifo_hwref_h__ +#define __nv_gt216_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_1 0x2144 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_gt216_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_flush_hwref.h new file mode 100644 index 000000000..e54c5efa8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_flush_hwref_h__ +#define __nv_gt216_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gt216_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..9b789158b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_graphics_nobundle_hwref_h__ +#define __nv_gt216_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_gt216_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_master_hwref.h new file mode 100644 index 000000000..5647a0bda --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_master_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_master_hwref_h__ +#define __nv_gt216_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 18:18 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 18:18 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_CE0 13:13 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_gt216_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_mmu_hwref.h new file mode 100644 index 000000000..ad8b944da --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_mmu_hwref.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_mmu_hwref_h__ +#define __nv_gt216_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+29):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 +#define NV_MMU_PTE_KIND_Z16 0x68 +#define NV_MMU_PTE_KIND_X8C24 0x44 + +#endif /* __nv_gt216_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..5c2773337 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_pwr_pri_hwref.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_pwr_pri_hwref_h__ +#define __nv_gt216_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 8 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 3:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 + +#endif /* __nv_gt216_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_ram_hwref.h new file mode 100644 index 000000000..efabff72e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_ram_hwref_h__ +#define __nv_gt216_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_gt216_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_therm_hwref.h new file mode 100644 index 000000000..de4226236 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_therm_hwref_h__ +#define __nv_gt216_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_gt216_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt216/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gt216/nv_timer_hwref.h new file mode 100644 index 000000000..c04c4cdda --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt216/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt216_timer_hwref_h__ +#define __nv_gt216_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gt216_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_bus_hwref.h new file mode 100644 index 000000000..d91f9e16d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_bus_hwref_h__ +#define __nv_gt218_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_gt218_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_fifo_hwref.h new file mode 100644 index 000000000..d6d53626e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_fifo_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_fifo_hwref_h__ +#define __nv_gt218_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_1 0x2144 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_gt218_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_flush_hwref.h new file mode 100644 index 000000000..21c4803d7 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_flush_hwref_h__ +#define __nv_gt218_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gt218_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..421c67973 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_graphics_nobundle_hwref_h__ +#define __nv_gt218_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_gt218_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_master_hwref.h new file mode 100644 index 000000000..531e81c59 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_master_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_master_hwref_h__ +#define __nv_gt218_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 18:18 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 18:18 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_CE0 13:13 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_gt218_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_mmu_hwref.h new file mode 100644 index 000000000..bfe6b200c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_mmu_hwref.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_mmu_hwref_h__ +#define __nv_gt218_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+29):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 +#define NV_MMU_PTE_KIND_Z16 0x68 +#define NV_MMU_PTE_KIND_X8C24 0x44 + +#endif /* __nv_gt218_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..abc381dcf --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_pwr_pri_hwref.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_pwr_pri_hwref_h__ +#define __nv_gt218_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 8 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 3:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 + +#endif /* __nv_gt218_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_ram_hwref.h new file mode 100644 index 000000000..4847bbd8b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_ram_hwref_h__ +#define __nv_gt218_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_gt218_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_therm_hwref.h new file mode 100644 index 000000000..fd78bbc92 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_therm_hwref_h__ +#define __nv_gt218_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_gt218_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gt218/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gt218/nv_timer_hwref.h new file mode 100644 index 000000000..de2cad49e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gt218/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gt218_timer_hwref_h__ +#define __nv_gt218_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_gt218_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp77/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp77/nv_bus_hwref.h new file mode 100644 index 000000000..165b7846e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp77/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp77_bus_hwref_h__ +#define __nv_mcp77_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_mcp77_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp77/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp77/nv_fifo_hwref.h new file mode 100644 index 000000000..4a0b2482d --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp77/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp77_fifo_hwref_h__ +#define __nv_mcp77_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_mcp77_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp77/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp77/nv_flush_hwref.h new file mode 100644 index 000000000..9785fb254 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp77/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp77_flush_hwref_h__ +#define __nv_mcp77_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_mcp77_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp77/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp77/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..3781bb8bf --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp77/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp77_graphics_nobundle_hwref_h__ +#define __nv_mcp77_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_mcp77_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp77/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp77/nv_master_hwref.h new file mode 100644 index 000000000..9ed7efec0 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp77/nv_master_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp77_master_hwref_h__ +#define __nv_mcp77_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_1 0x680 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x540 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_mcp77_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp77/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp77/nv_mmu_hwref.h new file mode 100644 index 000000000..5e041da70 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp77/nv_mmu_hwref.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp77_mmu_hwref_h__ +#define __nv_mcp77_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 +#define NV_MMU_PTE_KIND_Z16 0x68 +#define NV_MMU_PTE_KIND_X8C24 0x44 + +#endif /* __nv_mcp77_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp77/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp77/nv_ram_hwref.h new file mode 100644 index 000000000..aa409ed68 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp77/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp77_ram_hwref_h__ +#define __nv_mcp77_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_mcp77_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp77/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp77/nv_therm_hwref.h new file mode 100644 index 000000000..f9f6a3322 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp77/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp77_therm_hwref_h__ +#define __nv_mcp77_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_mcp77_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp77/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp77/nv_timer_hwref.h new file mode 100644 index 000000000..25fdff7cb --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp77/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp77_timer_hwref_h__ +#define __nv_mcp77_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_mcp77_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp79/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp79/nv_bus_hwref.h new file mode 100644 index 000000000..fb2cc6d3b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp79/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp79_bus_hwref_h__ +#define __nv_mcp79_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_mcp79_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp79/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp79/nv_fifo_hwref.h new file mode 100644 index 000000000..1181240a5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp79/nv_fifo_hwref.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp79_fifo_hwref_h__ +#define __nv_mcp79_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_mcp79_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp79/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp79/nv_flush_hwref.h new file mode 100644 index 000000000..7c00b389e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp79/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp79_flush_hwref_h__ +#define __nv_mcp79_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_mcp79_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp79/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp79/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..7d84afe34 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp79/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp79_graphics_nobundle_hwref_h__ +#define __nv_mcp79_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_mcp79_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp79/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp79/nv_master_hwref.h new file mode 100644 index 000000000..940dfd147 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp79/nv_master_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp79_master_hwref_h__ +#define __nv_mcp79_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_1 0x680 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x540 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_mcp79_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp79/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp79/nv_mmu_hwref.h new file mode 100644 index 000000000..869c41846 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp79/nv_mmu_hwref.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp79_mmu_hwref_h__ +#define __nv_mcp79_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 +#define NV_MMU_PTE_KIND_Z16 0x68 +#define NV_MMU_PTE_KIND_X8C24 0x44 + +#endif /* __nv_mcp79_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp79/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp79/nv_ram_hwref.h new file mode 100644 index 000000000..f9c9c6966 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp79/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp79_ram_hwref_h__ +#define __nv_mcp79_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_mcp79_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp79/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp79/nv_therm_hwref.h new file mode 100644 index 000000000..1293b77ff --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp79/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp79_therm_hwref_h__ +#define __nv_mcp79_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_mcp79_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp79/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp79/nv_timer_hwref.h new file mode 100644 index 000000000..74c25deec --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp79/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp79_timer_hwref_h__ +#define __nv_mcp79_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_mcp79_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_bus_hwref.h new file mode 100644 index 000000000..ebf68600b --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_bus_hwref.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_bus_hwref_h__ +#define __nv_mcp89_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 + +#endif /* __nv_mcp89_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_fifo_hwref.h new file mode 100644 index 000000000..75418f7cd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_fifo_hwref.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_fifo_hwref_h__ +#define __nv_mcp89_fifo_hwref_h__ + +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_PIO_ERROR 8:8 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 19:19 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 26:26 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_1 0x2144 +#define NV_PFIFO_RUNLIST 0x32ec +#define NV_PFIFO_PREEMPT 0x32fc + +#endif /* __nv_mcp89_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_flush_hwref.h new file mode 100644 index 000000000..edecdfed8 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_flush_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_flush_hwref_h__ +#define __nv_mcp89_flush_hwref_h__ + +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_mcp89_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..01cf24254 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_graphics_nobundle_hwref.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_graphics_nobundle_hwref_h__ +#define __nv_mcp89_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x400804 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x406800 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x405018 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SCC_INIT 0x405020 +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 + +#endif /* __nv_mcp89_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_master_hwref.h new file mode 100644 index 000000000..8e6e52688 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_master_hwref.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_master_hwref_h__ +#define __nv_mcp89_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 18:18 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 18:18 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_CE0 13:13 +#define NV_PMC_ENABLE_PFB 20:20 + +#endif /* __nv_mcp89_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_mmu_hwref.h new file mode 100644 index 000000000..a960cef9c --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_mmu_hwref.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_mmu_hwref_h__ +#define __nv_mcp89_mmu_hwref_h__ + +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+3):(0*32+3) +#define NV_MMU_PTE_APERTURE (0*32+5):(0*32+4) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+29):(1*32+17) +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+14):(1*32+8) +#define NV_MMU_PTE_KIND_INVALID 0x7f +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z24S8 16 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 20 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 21 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 22 +#define NV_MMU_PTE_KIND_S8Z24 32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x24 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x26 +#define NV_MMU_PTE_KIND_ZF32 0x40 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x54 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x55 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x56 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x60 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0x64 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0x65 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0x66 +#define NV_MMU_PTE_KIND_Z16 0x68 +#define NV_MMU_PTE_KIND_X8C24 0x44 + +#endif /* __nv_mcp89_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..93fbfb921 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_pwr_pri_hwref.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_pwr_pri_hwref_h__ +#define __nv_mcp89_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 15:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 3:0 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 + +#endif /* __nv_mcp89_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_ram_hwref.h new file mode 100644 index 000000000..91725b75f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_ram_hwref.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_ram_hwref_h__ +#define __nv_mcp89_ram_hwref_h__ + +#define NV_RAMFC_SUBDEVICE (31*32+31):(31*32+0) +#define NV_RAMFC_SEMAPHOREA (0x23*32+31):(0x23*32+0) +#define NV_RAMFC_SEMAPHOREB (0x24*32+31):(0x24*32+0) +#define NV_RAMFC_SEMAPHOREC (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_SIZE_VAL 0x100 + +#endif /* __nv_mcp89_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_therm_hwref.h new file mode 100644 index 000000000..f46924d8f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_therm_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_therm_hwref_h__ +#define __nv_mcp89_therm_hwref_h__ + +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 + +#endif /* __nv_mcp89_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/mcp89/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/mcp89/nv_timer_hwref.h new file mode 100644 index 000000000..7ce6e2c5e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/mcp89/nv_timer_hwref.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_mcp89_timer_hwref_h__ +#define __nv_mcp89_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 + +#endif /* __nv_mcp89_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/nv_chipids_hwref.h b/drm/nouveau/include/nvkm/hwref/nv_chipids_hwref.h new file mode 100644 index 000000000..484deeda5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/nv_chipids_hwref.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_chipids_hwref_h__ +#define __nv_chipids_hwref_h__ + +#define __nv_g80__ 0x80 +#define __nv_g84__ 0x84 +#define __nv_g86__ 0x86 +#define __nv_g92__ 0x92 +#define __nv_g94__ 0x94 +#define __nv_g96__ 0x96 +#define __nv_g98__ 0x98 +#define __nv_mcp77__ 0xaa +#define __nv_mcp79__ 0xac +#define __nv_mcp89__ 0xaf +#define __nv_g200__ 0xa0 +#define __nv_gt215__ 0xa3 +#define __nv_gt216__ 0xa5 +#define __nv_gt218__ 0xa8 +#define __nv_gf100__ 0xc0 +#define __nv_gf104__ 0xc4 +#define __nv_gf106__ 0xc3 +#define __nv_gf108__ 0xc1 +#define __nv_gf110__ 0xc8 +#define __nv_gf116__ 0xcf +#define __nv_gf114__ 0xce +#define __nv_gf117__ 0xd7 +#define __nv_gf119__ 0xd9 +#define __nv_gk104__ 0xe4 +#define __nv_gk106__ 0xe6 +#define __nv_gk107__ 0xe7 +#define __nv_gk110__ 0xf0 +#define __nv_gk110b__ 0xf1 +#define __nv_gk208b__ 0x106 +#define __nv_gk208__ 0x108 +#define __nv_gk20a__ 0xea +#define __nv_gm107__ 0x117 +#define __nv_gm108__ 0x118 +#define __nv_gm204__ 0x124 +#define __nv_gm206__ 0x126 +#define __nv_gm20b__ 0x12b +#define __nv_gpu_is_g8x(x) ((x)!=(x)\ + || ((x)==__nv_g98__)\ + || ((x)==__nv_g80__)\ + || ((x)==__nv_g84__)\ + || ((x)==__nv_g86__)\ + || ((x)==__nv_g96__)\ + || ((x)==__nv_g94__)\ + || ((x)==__nv_g92__)\ + ) + +#define __nv_gpu_is_tesla(x) ((x)!=(x)\ + || ((x)==__nv_mcp79__)\ + || ((x)==__nv_mcp77__)\ + || ((x)==__nv_mcp89__)\ + || ((x)==__nv_g200__)\ + || ((x)==__nv_gt215__)\ + || ((x)==__nv_gt216__)\ + || ((x)==__nv_gt218__)\ + ) + +#define __nv_gpu_is_fermi(x) ((x)!=(x)\ + || ((x)==__nv_gf100__)\ + || ((x)==__nv_gf110__)\ + || ((x)==__nv_gf106__)\ + || ((x)==__nv_gf104__)\ + || ((x)==__nv_gf117__)\ + || ((x)==__nv_gf108__)\ + || ((x)==__nv_gf114__)\ + || ((x)==__nv_gf119__)\ + || ((x)==__nv_gf116__)\ + ) + +#define __nv_gpu_is_kepler(x) ((x)!=(x)\ + || ((x)==__nv_gk104__)\ + || ((x)==__nv_gk106__)\ + || ((x)==__nv_gk107__)\ + || ((x)==__nv_gk110b__)\ + || ((x)==__nv_gk110__)\ + || ((x)==__nv_gk208__)\ + || ((x)==__nv_gk208b__)\ + || ((x)==__nv_gk20a__)\ + ) + +#define __nv_gpu_is_maxwell(x) ((x)!=(x)\ + || ((x)==__nv_gm20b__)\ + || ((x)==__nv_gm204__)\ + || ((x)==__nv_gm107__)\ + || ((x)==__nv_gm206__)\ + || ((x)==__nv_gm108__)\ + ) + +#endif /* __nv_chipids_hwref_h__ */ |