diff options
author | Alexandre Courbot <acourbot@nvidia.com> | 2016-02-12 14:19:27 +0900 |
---|---|---|
committer | Alexandre Courbot <acourbot@nvidia.com> | 2016-03-12 11:02:07 +0900 |
commit | 8cf71d670cad527f400d90172c5c028a2646531a (patch) | |
tree | e3c3e997e4a41fd986e3e4bb0c59af9ab8dc4452 | |
parent | 720e3dd79662fdaf396885b2f170d4cc416d3275 (diff) | |
download | nouveau-8cf71d670cad527f400d90172c5c028a2646531a.tar.gz |
clk/gk20a: only restore divider to 1:1 if needed
Only restore the 1:1 divider if it is not set already. Also use the
proper masks for this operation and add a second write as done in the
Android code.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
-rw-r--r-- | drm/nouveau/nvkm/subdev/clk/gk20a.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drm/nouveau/nvkm/subdev/clk/gk20a.c index e72e20a0d..0746bb3e3 100644 --- a/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -429,9 +429,16 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) /* restore out divider 1:1 */ val = nvkm_rd32(device, GPC2CLK_OUT); - val &= ~GPC2CLK_OUT_VCODIV_MASK; - udelay(2); - nvkm_wr32(device, GPC2CLK_OUT, val); + if ((val & GPC2CLK_OUT_VCODIV_MASK) != + (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT)) { + val &= ~GPC2CLK_OUT_VCODIV_MASK; + val |= GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT; + udelay(2); + nvkm_wr32(device, GPC2CLK_OUT, val); + /* Intentional 2nd write to assure linear divider operation */ + nvkm_wr32(device, GPC2CLK_OUT, val); + nvkm_rd32(device, GPC2CLK_OUT); + } /* slide up to new NDIV */ return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0; |