diff options
| author | Alexandre Courbot <acourbot@nvidia.com> | 2016-06-01 17:39:20 +0900 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2016-07-06 06:55:28 +1000 |
| commit | 5539cb1df1d8f1cbb373c8b66a849df9e2caab46 (patch) | |
| tree | 1593cded0cd9b18d1dfd67864ef409335dcd7297 | |
| parent | 256213c3463cb7d09a8f8d5a95e45689b17948d3 (diff) | |
| download | nouveau-5539cb1df1d8f1cbb373c8b66a849df9e2caab46.tar.gz | |
clk/gk20a: properly protect macro argument
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | drm/nouveau/nvkm/subdev/clk/gk20a.c | 2 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/subdev/clk/gm20b.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drm/nouveau/nvkm/subdev/clk/gk20a.c index 5f0ee24e3..d633669b5 100644 --- a/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -31,7 +31,7 @@ #define KHZ (1000) #define MHZ (KHZ * 1000) -#define MASK(w) ((1 << w) - 1) +#define MASK(w) ((1 << (w)) - 1) #define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) #define GPCPLL_CFG_ENABLE BIT(0) diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c index 71b2bbb61..274a74c14 100644 --- a/drm/nouveau/nvkm/subdev/clk/gm20b.c +++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c @@ -29,7 +29,7 @@ #define KHZ (1000) #define MHZ (KHZ * 1000) -#define MASK(w) ((1 << w) - 1) +#define MASK(w) ((1 << (w)) - 1) #define BYPASSCTRL_SYS (SYS_GPCPLL_CFG_BASE + 0x340) #define BYPASSCTRL_SYS_GPCPLL_SHIFT 0 |