diff options
author | Alexandre Courbot <acourbot@nvidia.com> | 2016-02-12 11:17:41 +0900 |
---|---|---|
committer | Alexandre Courbot <acourbot@nvidia.com> | 2016-02-26 10:24:28 +0900 |
commit | 7bc33684d52099cf03b3aa23a3b169f237267c3d (patch) | |
tree | 21a281d4ddb8cbf058e0f28f885d7d489e7c4e93 | |
parent | b086c268a06b7c8624c281948fd71e87cd87a402 (diff) | |
download | nouveau-7bc33684d52099cf03b3aa23a3b169f237267c3d.tar.gz |
gk20a: split init
-rw-r--r-- | drm/nouveau/nvkm/subdev/clk/gk20a.c | 43 | ||||
-rw-r--r-- | drm/nouveau/nvkm/subdev/clk/gk20a.h | 4 |
2 files changed, 33 insertions, 14 deletions
diff --git a/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drm/nouveau/nvkm/subdev/clk/gk20a.c index f0944b9b9..c7cbce180 100644 --- a/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -589,30 +589,45 @@ gk20a_clk = { }; int -gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +_gk20a_clk_ctor(struct nvkm_device * device, int index, + const struct nvkm_clk_func *func, + const struct gk20a_clk_pllg_params *params, + struct gk20a_clk *clk) { struct nvkm_device_tegra *tdev = device->func->tegra(device); - struct gk20a_clk *clk; - int ret, i; - - if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) - return -ENOMEM; - *pclk = &clk->base; + int ret; + int i; /* Finish initializing the pstates */ - for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { - INIT_LIST_HEAD(&gk20a_pstates[i].list); - gk20a_pstates[i].pstate = i + 1; + /* TODO duplicate pstate array? */ + for (i = 0; i < func->nr_pstates; i++) { + INIT_LIST_HEAD(&func->pstates[i].list); + func->pstates[i].pstate = i + 1; } - clk->params = &gk20a_pllg_params; + clk->params = params; clk->parent_rate = clk_get_rate(tdev->clk); + ret = nvkm_clk_ctor(func, device, index, true, &clk->base); + nvkm_info(&clk->base.subdev, "parent clock rate: %d Khz\n", + clk->parent_rate / KHZ); + clk->pl_to_div = pl_to_div; clk->div_to_pl = div_to_pl; - ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base); - nvkm_info(&clk->base.subdev, "parent clock rate: %d Khz\n", - clk->parent_rate / KHZ); return ret; } + +int +gk20a_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) +{ + struct gk20a_clk *clk; + + if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) + return -ENOMEM; + *pclk = &clk->base; + + return _gk20a_clk_ctor(device, index, &gk20a_clk, &gk20a_pllg_params, + clk); + +} diff --git a/drm/nouveau/nvkm/subdev/clk/gk20a.h b/drm/nouveau/nvkm/subdev/clk/gk20a.h index 3de5731fe..d6dcdb595 100644 --- a/drm/nouveau/nvkm/subdev/clk/gk20a.h +++ b/drm/nouveau/nvkm/subdev/clk/gk20a.h @@ -124,6 +124,10 @@ struct gk20a_clk { #define GK20A_CLK_GPC_MDIV 1000 +int _gk20a_clk_ctor(struct nvkm_device * device, int index, + const struct nvkm_clk_func *func, + const struct gk20a_clk_pllg_params *params, + struct gk20a_clk *clk); void gk20a_pllg_read_mnp(struct nvkm_clk *clk, struct gk20a_pll *pll); int gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate); void gk20a_pllg_enable(struct gk20a_clk *clk); |