diff options
author | Alexandre Courbot <acourbot@nvidia.com> | 2016-02-04 16:20:10 +0900 |
---|---|---|
committer | Alexandre Courbot <acourbot@nvidia.com> | 2016-02-26 10:24:28 +0900 |
commit | c2d2c19d6899b641458ee2c528944f11e7bfd1f3 (patch) | |
tree | f5eb783a057a351b5b6378d367e4ccb2a8fa6260 | |
parent | 9622008e9a58984c2eb09e0806c31bc2a887f787 (diff) | |
download | nouveau-c2d2c19d6899b641458ee2c528944f11e7bfd1f3.tar.gz |
remove unneeded function
-rw-r--r-- | drm/nouveau/nvkm/subdev/clk/gm20b.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c index bd52021df..3da3912c1 100644 --- a/drm/nouveau/nvkm/subdev/clk/gm20b.c +++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c @@ -169,12 +169,6 @@ static u32 gm20b_pllg_get_interim_pldiv(u32 old, u32 new) return min(old | BIT(ffs(new) - 1), new | BIT(ffs(old) - 1)); } -static void -gm20b_pllg_read_mnp(struct gm20b_clk *clk) -{ - gk20a_pllg_read_mnp(&clk->base, &clk->gpcpll.pll); -} - static u32 gm20b_pllg_calc_rate(u32 ref_rate, struct gk20a_pll *pll) { @@ -1110,7 +1104,7 @@ gm20b_clk_read(struct nvkm_clk *base, enum nv_clk_src src) case nv_clk_src_crystal: return device->crystal; case nv_clk_src_gpc: - gm20b_pllg_read_mnp(clk); + gk20a_pllg_read_mnp(&clk->base, &clk->gpcpll.pll); return gm20b_pllg_calc_rate(clk->parent_rate, &clk->gpcpll.pll) / GM20B_CLK_GPC_MDIV; default: |