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| author | Xia Yang <xiay@nvidia.com> | 2016-02-25 17:59:08 +0900 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2016-02-26 09:10:12 +1000 |
| commit | 4e404e403fdb54cd27002b84194609f446355bb8 (patch) | |
| tree | 188813d666fd9c81e7ace8a65cc9dd0d4e32be7b /drm/nouveau/dispnv04 | |
| parent | a1b10673ecfcb2ef156a90502dce4ce8a55924f6 (diff) | |
| download | nouveau-4e404e403fdb54cd27002b84194609f446355bb8.tar.gz | |
fifo/gk104: fix chid bit mask
Fix the channel id bit mask in FIFO schedule timeout error handling.
FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000.
FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff.
Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drm/nouveau/dispnv04')
0 files changed, 0 insertions, 0 deletions