diff options
| author | Ken Adams <tinsulpop@gmail.com> | 2015-10-20 14:49:37 -0400 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2015-11-10 16:42:20 +0900 |
| commit | 0d97f256240426be4dfc318d2d35c3ea2d1c659a (patch) | |
| tree | 00ecfb1132a9b1e24c129075823b20c14ed40dc4 /drm/nouveau/include/nvkm/hwref/gk110b | |
| parent | d5fbab716a0e0f74a759b38c44c2ba115dfee700 (diff) | |
| download | nouveau-0d97f256240426be4dfc318d2d35c3ea2d1c659a.tar.gz | |
hwref: hardware reference headers
These headers are generated from NVIDIA-internal hardware
manuals. For this check-in all chips Nouveau supports
>= nv50/g80 are included.
Signed-off-by: Ken Adams <kadams@nvidia.com>
Diffstat (limited to 'drm/nouveau/include/nvkm/hwref/gk110b')
22 files changed, 2543 insertions, 0 deletions
diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_bus_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_bus_hwref.h new file mode 100644 index 000000000..348898c65 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_bus_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_bus_hwref_h__ +#define __nv_gk110b_bus_hwref_h__ + +#define NV_PBUS_INTR_0 0x1100 +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_INTR_EN_0 0x1140 +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 +#define NV_PBUS_BAR1_BLOCK 0x1704 +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 +#define NV_PBUS_BAR2_BLOCK 0x1714 +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0 +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 1 +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 + +#endif /* __nv_gk110b_bus_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ce2_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ce2_pri_hwref.h new file mode 100644 index 000000000..d6015ddb5 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ce2_pri_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ce2_pri_hwref_h__ +#define __nv_gk110b_ce2_pri_hwref_h__ + +#define NV_PCE2_COP2_INTR_STATUS 0x106908 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE 0:0 +#define NV_PCE2_COP2_INTR_STATUS_BLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE 1:1 +#define NV_PCE2_COP2_INTR_STATUS_NONBLOCKPIPE_RESET 1 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR 2:2 +#define NV_PCE2_COP2_INTR_STATUS_LAUNCHERR_RESET 1 + +#endif /* __nv_gk110b_ce2_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_addendum_hwref.h new file mode 100644 index 000000000..742a9f0bd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_addendum_hwref.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ctxsw_prog_addendum_hwref_h__ +#define __nv_gk110b_ctxsw_prog_addendum_hwref_h__ + +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 + +#endif /* __nv_gk110b_ctxsw_prog_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_hwref.h new file mode 100644 index 000000000..082450ada --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ctxsw_prog_hwref.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ctxsw_prog_hwref_h__ +#define __nv_gk110b_ctxsw_prog_hwref_h__ + +#define NV_CTXSW_FECS_HEADER 0x100 +#define NV_CTXSW_MAIN_IMAGE_NUM_GPCS 8 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_COUNT 16 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_LO 20 +#define NV_CTXSW_MAIN_IMAGE_PRI_PATCH_ADR_HI 24 +#define NV_CTXSW_MAIN_IMAGE_ZCULL 28 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER 2 +#define NV_CTXSW_MAIN_IMAGE_ZCULL_PTR 32 +#define NV_CTXSW_MAIN_IMAGE_PM 0x28 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE 2:0 +#define NV_CTXSW_MAIN_IMAGE_PM_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE 5:3 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_NO_CTXSW 0 +#define NV_CTXSW_MAIN_IMAGE_SMPC_MODE_CTXSW 1 +#define NV_CTXSW_MAIN_IMAGE_PM_PTR 0x2c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS 0x3c +#define NV_CTXSW_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES 3:3 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS 0x60 +#define NV_CTXSW_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL 0:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG 0xa0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE 1:0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL 0 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP 2 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO 0xa4 +#define NV_CTXSW_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI 0xa8 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL 0xec +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_OFFSET 15:0 +#define NV_CTXSW_MAIN_EXTENDED_BUFFER_CTL_SIZE 23:16 +#define NV_CTXSW_MAIN_IMAGE_NUM_SAVE_OPERATIONS 0xf4 +#define NV_CTXSW_MAIN_IMAGE_NUM_RESTORE_OPERATIONS 0xf8 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE 0xfc +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_MAIN_IMAGE_MAGIC_VALUE_V_VALUE 0x600dc0de +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL 12 +#define NV_CTXSW_LOCAL_PRIV_REGISTER_CTL_OFFSET 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO 0xf4 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_NUM_PPCS 15:0 +#define NV_CTXSW_LOCAL_IMAGE_PPC_INFO_PPC_MASK 31:16 +#define NV_CTXSW_LOCAL_IMAGE_NUM_TPCS 0xf8 +#define NV_CTXSW_LOCAL_MAGIC_VALUE 0xfc +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V 31:0 +#define NV_CTXSW_LOCAL_MAGIC_VALUE_V_VALUE 0xad0becab +#define NV_CTXSW_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES 0x100 +#define NV_CTXSW_EXTENDED_MARKER_SIZE_IN_BYTES 4 +#define NV_CTXSW_EXTENDED_NUM_SMPC_QUADRANTS 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE 4 +#define NV_CTXSW_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE 5 + +#endif /* __nv_gk110b_ctxsw_prog_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_fb_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_fb_hwref.h new file mode 100644 index 000000000..24b5a2201 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_fb_hwref.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_fb_hwref_h__ +#define __nv_gk110b_fb_hwref_h__ + +#define NV_PFB_PRI_MMU_CTRL 0x100c80 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0 +#define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 1 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 +#define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x100cb8 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0 +#define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 +#define NV_PFB_PRI_MMU_INVALIDATE 0x100cbc +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 + +#endif /* __nv_gk110b_fb_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_fifo_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_fifo_hwref.h new file mode 100644 index 000000000..b718bb508 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_fifo_hwref.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_fifo_hwref_h__ +#define __nv_gk110b_fifo_hwref_h__ + +#define NV_PFIFO_BAR1_BASE 0x2254 +#define NV_PFIFO_BAR1_BASE_PTR 27:0 +#define NV_PFIFO_BAR1_BASE_VALID 28:28 +#define NV_PFIFO_BAR1_BASE_PTR_ALIGN_SHIFT 12 +#define NV_PCCSR_CHANNEL_INST(i) (0x800000+(i)*8) +#define NV_PCCSR_CHANNEL_INST__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0 +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 +#define NV_PCCSR_CHANNEL(i) (0x800004+(i)*8) +#define NV_PCCSR_CHANNEL__SIZE_1 0x1000 +#define NV_PCCSR_CHANNEL_ENABLE 0:0 +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 +#define NV_PCCSR_CHANNEL_RUNLIST 19:16 +#define NV_PCCSR_CHANNEL_STATUS 27:24 +#define NV_PCCSR_CHANNEL_BUSY 28:28 +#define NV_PFIFO_RUNLIST_BASE 0x2270 +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0 +#define NV_PFIFO_RUNLIST 0x2274 +#define NV_PFIFO_RUNLIST_ID 23:20 +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x2280+(i)*8) +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST(i) (0x2284+(i)*8) +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 7 +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 +#define NV_PFIFO_RUNLIST_TIMESLICE(i) (0x2310+(i)*4) +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMEOUT_128 0x80 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_RUNLIST_TIMESLICE_TIMESCALE_3 3 +#define NV_PFIFO_RUNLIST_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PB_TIMESLICE(i) (0x2350+(i)*4) +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT 7:0 +#define NV_PFIFO_PB_TIMESLICE_TIMEOUT_16 16 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE 15:12 +#define NV_PFIFO_PB_TIMESLICE_TIMESCALE_0 0 +#define NV_PFIFO_PB_TIMESLICE_ENABLE 28:28 +#define NV_PFIFO_PBDMA_MAP(i) (0x2390+(i)*4) +#define NV_PFIFO_INTR_0 0x2100 +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_PIO_ERROR 4:4 +#define NV_PFIFO_INTR_0_PIO_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT 23:23 +#define NV_PFIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET 1 +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 1 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT 27:27 +#define NV_PFIFO_INTR_0_DROPPED_MMU_FAULT_RESET 1 +#define NV_PFIFO_INTR_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 1 +#define NV_PFIFO_INTR_EN_0 0x2140 +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 +#define NV_PFIFO_INTR_EN_0_MMU_FAULT 28:28 +#define NV_PFIFO_INTR_EN_1 0x2528 +#define NV_PFIFO_INTR_BIND_ERROR 0x252c +#define NV_PFIFO_INTR_SCHED_ERROR 0x254c +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 10 +#define NV_PFIFO_INTR_CHSW_ERROR 0x256c +#define NV_PFIFO_INTR_MMU_FAULT_ID 0x259c +#define NV_PFIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS 0 +#define NV_PFIFO_INTR_MMU_FAULT_INST(i) (0x2800+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR 27:0 +#define NV_PFIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT 12 +#define NV_PFIFO_INTR_MMU_FAULT_LO(i) (0x2804+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_HI(i) (0x2808+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO(i) (0x280c+(i)*16) +#define NV_PFIFO_INTR_MMU_FAULT_INFO_TYPE 3:0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID 6:6 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC 0 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB 1 +#define NV_PFIFO_INTR_MMU_FAULT_INFO_CLIENT 12:8 +#define NV_PFIFO_INTR_PBDMA_ID 0x25a0 +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 3 +#define NV_PFIFO_INTR_RUNLIST 0x2a00 +#define NV_PFIFO_FB_TIMEOUT 0x2a04 +#define NV_PFIFO_FB_TIMEOUT_PERIOD 29:0 +#define NV_PFIFO_FB_TIMEOUT_PERIOD_MAX 0x3fffffff +#define NV_PFIFO_PB_TIMEOUT 0x2a08 +#define NV_PFIFO_PB_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ENG_TIMEOUT 0x2a0c +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 +#define NV_PFIFO_ERROR_SCHED_DISABLE 0x262c +#define NV_PFIFO_SCHED_DISABLE 0x2630 +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) +#define NV_PFIFO_PREEMPT 0x2634 +#define NV_PFIFO_PREEMPT_ID 11:0 +#define NV_PFIFO_PREEMPT_PENDING 20:20 +#define NV_PFIFO_PREEMPT_TYPE 25:24 +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0 +#define NV_PFIFO_PREEMPT_TYPE_TSG 1 +#define NV_PFIFO_TRIGGER_MMU_FAULT(i) (0x2a30+(i)*4) +#define NV_PFIFO_TRIGGER_MMU_FAULT_ID 4:0 +#define NV_PFIFO_TRIGGER_MMU_FAULT_ENABLE 8:8 +#define NV_PFIFO_ENGINE_STATUS(i) (0x2640+(i)*8) +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 8 +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 1 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 5 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 6 +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 7 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0 +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 1 +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 1 +#define NV_PFIFO_PBDMA_STATUS(i) (0x3080+(i)*4) +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 3 +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 1 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 5 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 6 +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 7 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0 +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 1 + +#endif /* __nv_gk110b_fifo_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_flush_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_flush_hwref.h new file mode 100644 index 000000000..55e5a26a4 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_flush_hwref.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_flush_hwref_h__ +#define __nv_gk110b_flush_hwref_h__ + +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x70004 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 1 +#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 +#define NV_UFLUSH_L2_FLUSH_DIRTY 0x70010 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0 +#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 1 +#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 +#define NV_UFLUSH_FB_FLUSH 0x70000 +#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 +#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 1 +#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 + +#endif /* __nv_gk110b_flush_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_graphics_nobundle_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_graphics_nobundle_hwref.h new file mode 100644 index 000000000..fdd4f4403 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_graphics_nobundle_hwref.h @@ -0,0 +1,856 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_graphics_nobundle_hwref_h__ +#define __nv_gk110b_graphics_nobundle_hwref_h__ + +#define NV_PGRAPH_INTR 0x400100 +#define NV_PGRAPH_INTR_NOTIFY 0:0 +#define NV_PGRAPH_INTR_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE 1:1 +#define NV_PGRAPH_INTR_SEMAPHORE_RESET 1 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT 2:2 +#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 +#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 +#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 1 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 +#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 1 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 +#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 1 +#define NV_PGRAPH_INTR_FECS_ERROR 19:19 +#define NV_PGRAPH_INTR_FECS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 +#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 1 +#define NV_PGRAPH_INTR_EXCEPTION 21:21 +#define NV_PGRAPH_INTR_EXCEPTION_RESET 1 +#define NV_PGRAPH_INTR_EN 0x40013c +#define NV_PGRAPH_FECS_INTR 0x400144 +#define NV_PGRAPH_EXCEPTION 0x400108 +#define NV_PGRAPH_EXCEPTION_FE 0:0 +#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 +#define NV_PGRAPH_EXCEPTION_DS 4:4 +#define NV_PGRAPH_EXCEPTION_GPC 24:24 +#define NV_PGRAPH_EXCEPTION1 0x400118 +#define NV_PGRAPH_EXCEPTION1_GPC 31:0 +#define NV_PGRAPH_EXCEPTION2 0x40011c +#define NV_PGRAPH_EXCEPTION_EN 0x400138 +#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 +#define NV_PGRAPH_EXCEPTION1_EN 0x400130 +#define NV_PGRAPH_EXCEPTION2_EN 0x400134 +#define NV_PGRAPH_CLASS_ERROR 0x400110 +#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 +#define NV_PGRAPH_NONSTALL_INTR 0x400120 +#define NV_PGRAPH_NONSTALL_INTR_TRAP 1:1 +#define NV_PGRAPH_GRFIFO_CONTROL 0x400500 +#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 +#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 +#define NV_PGRAPH_GRFIFO_STATUS 0x400504 +#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 +#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 +#define NV_PGRAPH_TRAPPED_DATA_LOW 0x400708 +#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x40070c +#define NV_PGRAPH_STATUS 0x400700 +#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 +#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0 +#define NV_PGRAPH_STATUS_MASK 0x400610 +#define NV_PGRAPH_STATUS1 0x400604 +#define NV_PGRAPH_STATUS2 0x400608 +#define NV_PGRAPH_ENGINE_STATUS 0x40060c +#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 +#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 1 +#define NV_PGRAPH_ACTIVITY0 0x400380 +#define NV_PGRAPH_ACTIVITY1 0x400384 +#define NV_PGRAPH_ACTIVITY2 0x400388 +#define NV_PGRAPH_ACTIVITY4 0x400390 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x400200 +#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 +#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x400204 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x400208 +#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR 0x404000 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS 0x404150 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x404154 +#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 +#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK 0x404158 +#define NV_PGRAPH_PRI_FE_PWR_MODE 0x404170 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 2 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0 +#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 1 +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x404200+((i)*4)) +#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x404488 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 1 +#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x40448c +#define NV_PGRAPH_PRI_MME_HWW_ESR 0x404490 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x404600 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0 0x409040 +#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1 0x409044 +#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE 0x40904c +#define NV_PGRAPH_PRI_FECS_FALCON_OS 0x409080 +#define NV_PGRAPH_PRI_FECS_FALCON_RM 0x409084 +#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO 0x409094 +#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL 0x4090a4 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL 0x409100 +#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC 0x409104 +#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG 0x409108 +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL 0x40910c +#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE 0x409110 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS 0x409114 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD 0x409118 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS 0x40911c +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i) (0x409180+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i) (0x409184+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i) (0x409188+((i)*16)) +#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i) (0x4091c0+((i)*8)) +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i) (0x4091c4+((i)*8)) +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX 0x409b00 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM 0 +#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_NEW_CTX 0x409b04 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID 31:31 +#define NV_PGRAPH_PRI_FECS_METHOD_DATA 0x409500 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH 0x409504 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR 11:0 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER 3 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE 4 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 16 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 9 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN 21 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 22 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x25 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x30 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x31 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x32 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW 0x38 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW 0x39 +#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x21 +#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE 0x409420 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0 0x409c00 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1 0x409400 +#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY 12:12 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS 0x409c18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR 0x409c20 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE 0x409c24 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG 19:19 +#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL 0x409614 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT 0:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT 1:1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT 2:2 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET 6:6 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET 10:10 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED 0 +#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED 1 +#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x40960c +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i) (0x409800+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1 16 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS 1 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL 2 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x4098c0+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i) (0x409840+((i)*4)) +#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE 31:0 +#define NV_PGRAPH_PRI_FECS_FS 0x409604 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS 4:0 +#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS 20:16 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON 0x409620 +#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_FECS_RC_LANES 0x409880 +#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR 0x409a24 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR 0x409a0c +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR 27:0 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET 29:28 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD 0x409a10 +#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD 4:0 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0 0x40780c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1 0x407810 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2 0x407814 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3 0x407818 +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4 0x40781c +#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5 0x407820 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG 0x4078bc +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_PD_HWW_ESR 0x406018 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i) (0x406028+((i)*4)) +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1 4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0 3:0 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1 7:4 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2 11:8 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3 15:12 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4 19:16 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5 23:20 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6 27:24 +#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7 31:28 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0 0x4064c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE 31:31 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN 1 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS 0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 0x4064c4 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES 15:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT 0xffff +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT 26:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY 0x80 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2 0x4064c8 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT 11:0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_TOKEN_LIMIT_INIT 0x7c0 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT 27:16 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY 32 +#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS 0x5a2 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL 0x4064cc +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_PD_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE(i) (0x4064d0+((i)*4)) +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE__SIZE_1 8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_DIST_SKIP_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i) (0x406800+((i)*4)) +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i) (0x406c00+((i)*4)) +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1 0x100 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK 7:0 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK 15:8 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK 23:16 +#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK 31:24 +#define NV_PGRAPH_PRI_DS_DEBUG 0x405800 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE 27:27 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R 0x405804 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G 0x405808 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B 0x40580c +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A 0x405810 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT 0x405814 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL 6:0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO 1 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE 2 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32 4 +#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8 0x28 +#define NV_PGRAPH_PRI_DS_ZBC_Z 0x405818 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL 31:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT 0x40581c +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID 0 +#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX 0x405820 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL 3:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD 0x405824 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT 0:0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z 1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION 1:1 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE 0 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER 2:2 +#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE 1 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC 0x405830 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE 27:16 +#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE 11:0 +#define NV_PGRAPH_PRI_DS_HWW_ESR 0x405840 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK 1 +#define NV_PGRAPH_PRI_DS_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK 0x405844 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR 0:0 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR 1:1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR 2:2 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR 3:3 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR 4:4 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR 5:5 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR 6:6 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR 7:7 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR 8:8 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR 9:9 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR 10:10 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR 11:11 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR 12:12 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR 13:13 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR 14:14 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR 15:15 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR 16:16 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR 17:17 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR 18:18 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR 19:19 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR 20:20 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR 21:21 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR 22:22 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR 23:23 +#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT 1 +#define NV_PGRAPH_PRI_DS_MPIPE_STATUS 0x405858 +#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i) (0x405870+((i)*4)) +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE 0x408004 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE 0x408008 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE 0x40800c +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS 8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL 0x408010 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY 0x100 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES 15:8 +#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID 31:31 +#define NV_PGRAPH_PRI_SCC_INIT 0x40802c +#define NV_PGRAPH_PRI_SCC_INIT_RAM 0:0 +#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR 0x408030 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN 31:31 +#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE 1 +#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x407020 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 +#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 1 +#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x407054 +#define NV_PGRAPH_PRI_CWD_FS 0x405b00 +#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 +#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE 0x502420 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x502c04 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1 0x502400 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC 0x502608 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON 0x502620 +#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ 7:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES 0x502880 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS 5:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i) (0x502910+((i)*0)) +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1 16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V 23:0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0 0 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x502c80 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x502c84 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x502c88 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x502c8c +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x502c90 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC 23:16 +#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x502c94 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS 0x500910 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS 8:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR 0x500914 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP 0x500918 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE 0x500920 +#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i) (0x500a04+((i)*32)) +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT 12:1 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH 28:16 +#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 16 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS 0x500c08 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i) (0x500c10+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x500c30+((i)*4)) +#define NV_PGRAPH_PRI_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK 7:0 +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS 0x500c8c +#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM 2:0 +#define NV_PGRAPH_PRI_GPC0_GCC_DBG 0x501000 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0 0x504500 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x504508 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x50450c +#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID 0x504088 +#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG 0x5044b0 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15 27:27 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG_CYA15_EN 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID 0x5044e8 +#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x504604 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x504608 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0 0x50460c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0 0x504610 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP 1:1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM 2:2 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0 0x504624 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0 0x504634 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR 0x504648 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE 0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x504650 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x50465c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x504658 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x504660 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x504664 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x504668 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x50466c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS 0x504670 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x504694 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0 0x504674 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1 0x504678 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2 0x50467c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3 0x504680 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4 0x504684 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5 0x504688 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6 0x50468c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7 0x504690 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG 0x504698 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID 15:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH 0x50469c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT 7:0 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION 11:8 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION_SMKEPLER_LP 12 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x5046a4 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x504730 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x504734 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x504738 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x50473c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x504740 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x504744 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x504748 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x50474c +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HALFCTL_CTRL 0x504770 +#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x50477c +#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0 0x504d00 +#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0 0x501d00 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM 0x503018 +#define NV_PGRAPH_PRI_GPC0_PPC0_PES_VSC_STREAM_MASTER_PE 0:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG 0x5030c0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_DEFAULT 0x218 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2 0x5030e4 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_START_OFFSET 15:0 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE 27:16 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_DEFAULT 0x648 +#define NV_PGRAPH_PRI_GPC0_PPC0_CBM_CONFIG2_SIZE_GRANULARITY 32 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL 0x41a100 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG 0x41a108 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL 0x41a10c +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i) (0x41a180+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i) (0x41a184+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i) (0x41a188+((i)*16)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1 4 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG 15:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i) (0x41a1c0+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS 7:2 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK 15:8 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW 24:24 +#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i) (0x41a1c4+((i)*8)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i) (0x41a800+((i)*4)) +#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE 31:0 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0 0x41ac80 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1 0x41ac84 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2 0x41ac88 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3 0x41ac8c +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN 0x41ac94 +#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC 23:16 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE 0x418808 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE 0x41880c +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B__PROD 0x30 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE 0x418810 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 12 +#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0 0x418b08 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1 0x418b0c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2 0x418b10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3 0x418b14 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4 0x418b18 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5 0x418b1c +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30 2:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31 7:5 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32 12:10 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33 17:15 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34 22:20 +#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35 27:25 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG 0x418bb8 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x418980 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x418984 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x418988 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23 30:28 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x41898c +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26 10:8 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27 14:12 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28 18:16 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29 22:20 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30 26:24 +#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31 30:28 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG 0x418c6c +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG 0x419000 +#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE 1:1 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE 0x419004 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL 0x419008 +#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES 7:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL 0x418880 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE 0:0 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT 1:1 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT 2:2 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN 4:3 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE 6:5 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE 29:28 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL 30:30 +#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE 31:31 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK 0x418890 +#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK 0x418894 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL 0x4188b0 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG 16:16 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR 0x4188b4 +#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD 0x4188b8 +#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 0x41c500 +#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 0x41cd00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0 0x419d00 +#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x419d0c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF 0x41980c +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x419848 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V 27:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID 28:28 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG 0x419c00 +#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0 0x419e10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER 31:31 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x419e44 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG 13:13 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR 14:14 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT 20:20 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x419e4c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT 1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x419e50 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE 5:5 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE 6:6 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x419ea4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED 0x419eac +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_MACRO_SCHED_LOCKBOOST_SIZE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK 0x419ec8 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH 0:0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE 1:1 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TILE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE 2:2 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_PHASE_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX 3:3 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TEX_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT 11:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_TEX_HASH_TIMEOUT_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK 16:16 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_SCH_TEXLOCK_DOT_T_UNLOCK_DISABLE 0 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL 0x419f70 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL 4:4 +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x419f7c +#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL 0:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC 0x41be08 +#define NV_PGRAPH_PRI_GPCS_PPCS_PES_VSC_VPC_FAST_MODE_SWITCH 2:2 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP0 0x41bf00 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP1 0x41bf04 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP2 0x41bf08 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP3 0x41bf0c +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP4 0x41bf10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_GPC_MAP5 0x41bf14 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG 0x41bfd0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_NUM_ENTRIES 20:16 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_NORMALIZED_SHIFT_VALUE 23:21 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG_COEFF5_MOD_VALUE 28:24 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP 0x41bfd4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE 23:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2 0x41bfe4 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF6_MOD_VALUE 4:0 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF7_MOD_VALUE 9:5 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF8_MOD_VALUE 14:10 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF9_MOD_VALUE 19:15 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF10_MOD_VALUE 24:20 +#define NV_PGRAPH_PRI_GPCS_PPCS_WWDX_MAP_TABLE_CONFIG2_COEFF11_MOD_VALUE 29:25 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG 0x41bec0 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE 28:28 +#define NV_PGRAPH_PRI_GPCS_PPCS_CBM_CONFIG_TIMESLICE_MODE_ENABLE 1 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS 0x410048 +#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2 0x41004c +#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3 0x410108 +#define NV_PGRAPH_PRI_BE0_CROP_STATUS1 0x410134 +#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0 0x410200 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION 0x410204 +#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN 0x410208 +#define NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0 0x410600 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS 0x408848 +#define NV_PGRAPH_PRI_BES_ZROP_STATUS2 0x40884c +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS 0x408850 +#define NV_PGRAPH_PRI_BES_ZROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_CROP_DEBUG3 0x408908 +#define NV_PGRAPH_PRI_BES_CROP_STATUS1 0x408934 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS 0x408958 +#define NV_PGRAPH_PRI_BES_CROP_SETTINGS_NUM_ACTIVE_FBPS 3:0 +#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0 0x408a00 +#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32 +#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 0xc0 +#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16 + +#endif /* __nv_gk110b_graphics_nobundle_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ltc_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ltc_hwref.h new file mode 100644 index 000000000..777a260ea --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ltc_hwref.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ltc_hwref_h__ +#define __nv_gk110b_ltc_hwref_h__ + +#define NV_PLTCG_LTC0_LTS0_INTR 0x141020 +#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x1410c8 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x141104 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 1 +#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 2 +#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x141200 +#define NV_PLTCG_LTC0_LTSS_INTR 0x140820 +#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x140828 +#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x140910 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x140914 +#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTC1_LTSS_G_ELPG 0x142828 +#define NV_PLTCG_LTC1_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0 0x142910 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1 0x142914 +#define NV_PLTCG_LTC1_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_INTR 0x17e820 +#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 +#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x17e828 +#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x17e8c8 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 1 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x17e8cc +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x17e8d0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 16:0 +#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0x1ffff +#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x17e8d4 +#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x17e8dc +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE 15:0 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 +#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_FBP 31:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x17e910 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x17e914 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 3 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 +#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x17e91c +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x17e924 +#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 +#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x17ea00 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x17ea44 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 3:0 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x17ea48+((i)*4)) +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x17ea58 +#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 +#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 11 + +#endif /* __nv_gk110b_ltc_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_master_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_master_hwref.h new file mode 100644 index 000000000..b75399f99 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_master_hwref.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_master_hwref_h__ +#define __nv_gk110b_master_hwref_h__ + +#define NV_PMC_BOOT_0 0 +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 +#define NV_PMC_INTR_0 0x100 +#define NV_PMC_INTR_0_PFIFO 8:8 +#define NV_PMC_INTR_0_PGRAPH 12:12 +#define NV_PMC_INTR_0_PMU 24:24 +#define NV_PMC_INTR_0_LTC 25:25 +#define NV_PMC_INTR_0_PBUS 28:28 +#define NV_PMC_INTR_0_PRIV_RING 30:30 +#define NV_PMC_INTR_1 0x104 +#define NV_PMC_INTR_MSK_0 0x640 +#define NV_PMC_INTR_MSK_0_PMU 24:24 +#define NV_PMC_INTR_MSK_1 0x644 +#define NV_PMC_INTR_MSK_1_PMU 24:24 +#define NV_PMC_INTR_EN_0 0x140 +#define NV_PMC_INTR_EN_0_INTA 1:0 +#define NV_PMC_INTR_EN_0_INTA_HARDWARE 1 +#define NV_PMC_INTR_EN_1 0x144 +#define NV_PMC_INTR_EN_1_INTA 1:0 +#define NV_PMC_INTR_EN_1_INTA_HARDWARE 1 +#define NV_PMC_INTR_LTC 0x17c +#define NV_PMC_ENABLE 0x200 +#define NV_PMC_ENABLE_XBAR 2:2 +#define NV_PMC_ENABLE_L2 3:3 +#define NV_PMC_ENABLE_PMEDIA 4:4 +#define NV_PMC_ENABLE_PRIV_RING 5:5 +#define NV_PMC_ENABLE_CE0 6:6 +#define NV_PMC_ENABLE_PFIFO 8:8 +#define NV_PMC_ENABLE_PGRAPH 12:12 +#define NV_PMC_ENABLE_PWR 13:13 +#define NV_PMC_ENABLE_PFB 20:20 +#define NV_PMC_ENABLE_CE2 21:21 +#define NV_PMC_ENABLE_BLG 27:27 +#define NV_PMC_ENABLE_PERFMON 28:28 +#define NV_PMC_ENABLE_HUB 29:29 +#define NV_PMC_ENABLE_PB 0x204 +#define NV_PMC_ENABLE_PB_0 0:0 +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) +#define NV_PMC_ELPG_ENABLE 0x20c +#define NV_PMC_ELPG_ENABLE_XBAR 2:2 +#define NV_PMC_ELPG_ENABLE_PFB 20:20 +#define NV_PMC_ELPG_ENABLE_HUB 29:29 + +#endif /* __nv_gk110b_master_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_mmu_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_mmu_hwref.h new file mode 100644 index 000000000..73ecfef6e --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_mmu_hwref.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_mmu_hwref_h__ +#define __nv_gk110b_mmu_hwref_h__ + +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0 +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 1 +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) +#define NV_MMU_PDE_SIZE_FULL 0 +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0 +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 1 +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) +#define NV_MMU_PDE_ADDRESS_SHIFT 12 +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0 +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) +#define NV_MMU_PTE_ADDRESS_SHIFT 12 +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) +#define NV_MMU_PTE_KIND_INVALID 0xff +#define NV_MMU_PTE_KIND_PITCH 0 +#define NV_MMU_PTE_KIND_Z16 1 +#define NV_MMU_PTE_KIND_Z16_2C 2 +#define NV_MMU_PTE_KIND_Z16_MS2_2C 3 +#define NV_MMU_PTE_KIND_Z16_MS4_2C 4 +#define NV_MMU_PTE_KIND_Z16_MS8_2C 5 +#define NV_MMU_PTE_KIND_Z16_MS16_2C 6 +#define NV_MMU_PTE_KIND_Z16_2Z 7 +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 8 +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 9 +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 10 +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 11 +#define NV_MMU_PTE_KIND_Z16_4CZ 12 +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 13 +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 14 +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 15 +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 16 +#define NV_MMU_PTE_KIND_S8Z24 17 +#define NV_MMU_PTE_KIND_S8Z24_1Z 18 +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 19 +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 20 +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 21 +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 22 +#define NV_MMU_PTE_KIND_S8Z24_2CZ 23 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 24 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 25 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 26 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 27 +#define NV_MMU_PTE_KIND_S8Z24_2CS 28 +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 29 +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 30 +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 31 +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 32 +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 +#define NV_MMU_PTE_KIND_Z24S8 0x46 +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a +#define NV_MMU_PTE_KIND_ZF32 0x7b +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe +#define NV_MMU_PTE_KIND_C32_2C 0xd8 +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 +#define NV_MMU_PTE_KIND_C32_2CBA 0xda +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 +#define NV_MMU_PTE_KIND_C64_2C 0xe6 +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 +#define NV_MMU_PTE_KIND_C64_2BRA 0xea +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 +#define NV_MMU_PTE_KIND_C128_2C 0xf4 +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb +#define NV_MMU_PTE_KIND_X8C24 0xfc +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb + +#endif /* __nv_gk110b_mmu_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_pbdma_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pbdma_hwref.h new file mode 100644 index 000000000..7118fb0ef --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pbdma_hwref.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_pbdma_hwref_h__ +#define __nv_gk110b_pbdma_hwref_h__ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 +#define NV_PPBDMA_GP_BASE(i) (0x40048+(i)*0x2000) +#define NV_PPBDMA_GP_BASE__SIZE_1 3 +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 +#define NV_PPBDMA_GP_BASE_RSVD 2:0 +#define NV_PPBDMA_GP_BASE_HI(i) (0x4004c+(i)*0x2000) +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 +#define NV_PPBDMA_GP_FETCH(i) (0x40050+(i)*0x2000) +#define NV_PPBDMA_GP_GET(i) (0x40014+(i)*0x2000) +#define NV_PPBDMA_GP_PUT(i) (0x40000+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH(i) (0x40054+(i)*0x2000) +#define NV_PPBDMA_PB_FETCH_HI(i) (0x40058+(i)*0x2000) +#define NV_PPBDMA_GET(i) (0x40018+(i)*0x2000) +#define NV_PPBDMA_GET_HI(i) (0x4001c+(i)*0x2000) +#define NV_PPBDMA_PUT(i) (0x4005c+(i)*0x2000) +#define NV_PPBDMA_PUT_HI(i) (0x40060+(i)*0x2000) +#define NV_PPBDMA_FORMATS(i) (0x4009c+(i)*0x2000) +#define NV_PPBDMA_FORMATS_GP 1:0 +#define NV_PPBDMA_FORMATS_GP_FERMI0 0 +#define NV_PPBDMA_FORMATS_PB 9:8 +#define NV_PPBDMA_FORMATS_PB_FERMI1 1 +#define NV_PPBDMA_FORMATS_MP 25:24 +#define NV_PPBDMA_FORMATS_MP_FERMI0 0 +#define NV_PPBDMA_PB_HEADER(i) (0x40084+(i)*0x2000) +#define NV_PPBDMA_PB_HEADER_PRIV 1:1 +#define NV_PPBDMA_PB_HEADER_PRIV_USER 0 +#define NV_PPBDMA_PB_HEADER_METHOD 13:2 +#define NV_PPBDMA_PB_HEADER_METHOD_ZERO 0 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL 18:16 +#define NV_PPBDMA_PB_HEADER_SUBCHANNEL_ZERO 0 +#define NV_PPBDMA_PB_HEADER_LEVEL 20:20 +#define NV_PPBDMA_PB_HEADER_LEVEL_MAIN 0 +#define NV_PPBDMA_PB_HEADER_FIRST 22:22 +#define NV_PPBDMA_PB_HEADER_TYPE 31:29 +#define NV_PPBDMA_PB_HEADER_TYPE_INC 1 +#define NV_PPBDMA_SUBDEVICE(i) (0x40094+(i)*0x2000) +#define NV_PPBDMA_SUBDEVICE_ID 11:0 +#define NV_PPBDMA_SUBDEVICE_STATUS 28:28 +#define NV_PPBDMA_SUBDEVICE_STATUS_ACTIVE 1 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA 29:29 +#define NV_PPBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 1 +#define NV_PPBDMA_METHOD0(i) (0x400c0+(i)*0x2000) +#define NV_PPBDMA_DATA0(i) (0x400c4+(i)*0x2000) +#define NV_PPBDMA_TARGET(i) (0x400ac+(i)*0x2000) +#define NV_PPBDMA_TARGET_ENGINE 4:0 +#define NV_PPBDMA_TARGET_ENGINE_SW 31 +#define NV_PPBDMA_ACQUIRE(i) (0x40030+(i)*0x2000) +#define NV_PPBDMA_ACQUIRE_RETRY_MAN 6:0 +#define NV_PPBDMA_ACQUIRE_RETRY_MAN_2 2 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP 10:7 +#define NV_PPBDMA_ACQUIRE_RETRY_EXP_2 2 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP 14:11 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EXP_MAX 15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN 30:15 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0xffff +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN 31:31 +#define NV_PPBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0 +#define NV_PPBDMA_STATUS(i) (0x40100+(i)*0x2000) +#define NV_PPBDMA_CHANNEL(i) (0x40120+(i)*0x2000) +#define NV_PPBDMA_HDR_SHADOW(i) (0x40118+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE(i) (0x40010+(i)*0x2000) +#define NV_PPBDMA_SIGNATURE_HW 15:0 +#define NV_PPBDMA_SIGNATURE_HW_VALID 0xface +#define NV_PPBDMA_SIGNATURE_SW 31:16 +#define NV_PPBDMA_SIGNATURE_SW_ZERO 0 +#define NV_PPBDMA_USERD(i) (0x40008+(i)*0x2000) +#define NV_PPBDMA_USERD_TARGET 1:0 +#define NV_PPBDMA_USERD_TARGET_VID_MEM 0 +#define NV_PPBDMA_USERD_ADDR 31:9 +#define NV_PPBDMA_USERD_HI(i) (0x4000c+(i)*0x2000) +#define NV_PPBDMA_USERD_HI_ADDR 7:0 +#define NV_PPBDMA_HCE_CTRL(i) (0x400e4+(i)*0x2000) +#define NV_PPBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 +#define NV_PPBDMA_TIMEOUT(i) (0x4012c+(i)*0x2000) +#define NV_PPBDMA_TIMEOUT__SIZE_1 3 +#define NV_PPBDMA_TIMEOUT_PERIOD 31:0 +#define NV_PPBDMA_TIMEOUT_PERIOD_MAX 0xffffffff +#define NV_PPBDMA_INTR_0(i) (0x40108+(i)*0x2000) +#define NV_PPBDMA_INTR_0_MEMREQ 0:0 +#define NV_PPBDMA_INTR_0_MEMACK_TIMEOUT 1:1 +#define NV_PPBDMA_INTR_0_MEMACK_EXTRA 2:2 +#define NV_PPBDMA_INTR_0_MEMDAT_TIMEOUT 3:3 +#define NV_PPBDMA_INTR_0_MEMDAT_EXTRA 4:4 +#define NV_PPBDMA_INTR_0_MEMFLUSH 5:5 +#define NV_PPBDMA_INTR_0_MEMOP 6:6 +#define NV_PPBDMA_INTR_0_LBCONNECT 7:7 +#define NV_PPBDMA_INTR_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_0_LBACK_TIMEOUT 9:9 +#define NV_PPBDMA_INTR_0_LBACK_EXTRA 10:10 +#define NV_PPBDMA_INTR_0_LBDAT_TIMEOUT 11:11 +#define NV_PPBDMA_INTR_0_LBDAT_EXTRA 12:12 +#define NV_PPBDMA_INTR_0_GPFIFO 13:13 +#define NV_PPBDMA_INTR_0_GPPTR 14:14 +#define NV_PPBDMA_INTR_0_GPENTRY 15:15 +#define NV_PPBDMA_INTR_0_GPCRC 16:16 +#define NV_PPBDMA_INTR_0_PBPTR 17:17 +#define NV_PPBDMA_INTR_0_PBENTRY 18:18 +#define NV_PPBDMA_INTR_0_PBCRC 19:19 +#define NV_PPBDMA_INTR_0_XBARCONNECT 20:20 +#define NV_PPBDMA_INTR_0_METHOD 21:21 +#define NV_PPBDMA_INTR_0_METHODCRC 22:22 +#define NV_PPBDMA_INTR_0_DEVICE 23:23 +#define NV_PPBDMA_INTR_0_SEMAPHORE 25:25 +#define NV_PPBDMA_INTR_0_ACQUIRE 26:26 +#define NV_PPBDMA_INTR_0_PRI 27:27 +#define NV_PPBDMA_INTR_0_NO_CTXSW_SEG 29:29 +#define NV_PPBDMA_INTR_0_PBSEG 30:30 +#define NV_PPBDMA_INTR_0_SIGNATURE 31:31 +#define NV_PPBDMA_INTR_1(i) (0x40148+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0(i) (0x4010c+(i)*0x2000) +#define NV_PPBDMA_INTR_EN_0_LBREQ 8:8 +#define NV_PPBDMA_INTR_EN_1(i) (0x4014c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL(i) (0x4013c+(i)*0x2000) +#define NV_PPBDMA_INTR_STALL_LBREQ 8:8 +#define NV_UDMA_NOP 8 + +#endif /* __nv_gk110b_pbdma_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringmaster_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringmaster_hwref.h new file mode 100644 index 000000000..e0afee067 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringmaster_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_pri_ringmaster_hwref_h__ +#define __nv_gk110b_pri_ringmaster_hwref_h__ + +#define NV_PPRIV_MASTER_RING_COMMAND 0x12004c +#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 1 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 2 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 3 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 8:6 +#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0 +#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x120048 +#define NV_PPRIV_MASTER_RING_START_RESULTS 0x120050 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 +#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 1 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x120058 +#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x12005c +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x120060 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 1 +#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x120074 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x120078 +#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 + +#endif /* __nv_gk110b_pri_ringmaster_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringstation_sys_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringstation_sys_hwref.h new file mode 100644 index 000000000..835889f63 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pri_ringstation_sys_hwref.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_pri_ringstation_sys_hwref_h__ +#define __nv_gk110b_pri_ringstation_sys_hwref_h__ + +#define NV_PPRIV_SYS_MASTER_SM_CONFIG(i) (0x122300+(i)*4) +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG 0x122204 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING 2:0 +#define NV_PPRIV_SYS_PRIV_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED 1 + +#endif /* __nv_gk110b_pri_ringstation_sys_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_proj_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_proj_hwref.h new file mode 100644 index 000000000..f181a9849 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_proj_hwref.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_proj_hwref_h__ +#define __nv_gk110b_proj_hwref_h__ + +#define NV_GPC_PRI_BASE 0x500000 +#define NV_GPC_PRI_SHARED_BASE 0x418000 +#define NV_GPC_PRI_STRIDE 0x8000 +#define NV_LTC_PRI_STRIDE 0x2000 +#define NV_LTS_PRI_STRIDE 0x400 +#define NV_HOST_NUM_PBDMA 3 +#define NV_SCAL_FAMILY_MAX_GPCS 32 +#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8 +#define NV_SCAL_LITTER_NUM_FBPS 6 +#define NV_SCAL_LITTER_NUM_GPCS 5 +#define NV_SCAL_LITTER_NUM_PES_PER_GPC 2 +#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2 +#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 3 +#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4 +#define NV_PPC_IN_GPC_BASE 0x3000 +#define NV_PPC_IN_GPC_STRIDE 0x200 +#define NV_ROP_PRI_BASE 0x410000 +#define NV_ROP_PRI_SHARED_BASE 0x408800 +#define NV_ROP_PRI_STRIDE 0x400 +#define NV_TPC_IN_GPC_BASE 0x4000 +#define NV_TPC_IN_GPC_SHARED_BASE 0x1800 +#define NV_TPC_IN_GPC_STRIDE 0x800 + +#endif /* __nv_gk110b_proj_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_pwr_pri_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pwr_pri_hwref.h new file mode 100644 index 000000000..d3cbbf97f --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_pwr_pri_hwref.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_pwr_pri_hwref_h__ +#define __nv_gk110b_pwr_pri_hwref_h__ + +#define NV_PPWR_FALCON_IRQSSET 0x10a000 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 1 +#define NV_PPWR_FALCON_IRQSCLR 0x10a004 +#define NV_PPWR_FALCON_IRQSTAT 0x10a008 +#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 +#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMODE 0x10a00c +#define NV_PPWR_FALCON_IRQMSET 0x10a010 +#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 +#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR 0x10a014 +#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 +#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 +#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 +#define NV_PPWR_FALCON_IRQMASK 0x10a018 +#define NV_PPWR_FALCON_IRQDEST 0x10a01c +#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 +#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 +#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 +#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 +#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 +#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 +#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 +#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 +#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 +#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 +#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 +#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 +#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 +#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 +#define NV_PPWR_FALCON_CURCTX 0x10a050 +#define NV_PPWR_FALCON_NXTCTX 0x10a054 +#define NV_PPWR_FALCON_MAILBOX0 0x10a040 +#define NV_PPWR_FALCON_MAILBOX1 0x10a044 +#define NV_PPWR_FALCON_ITFEN 0x10a048 +#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 +#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 1 +#define NV_PPWR_FALCON_IDLESTATE 0x10a04c +#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 +#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 +#define NV_PPWR_FALCON_OS 0x10a080 +#define NV_PPWR_FALCON_ENGCTL 0x10a0a4 +#define NV_PPWR_FALCON_CPUCTL 0x10a100 +#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 +#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 +#define NV_PPWR_FALCON_BOOTVEC 0x10a104 +#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 +#define NV_PPWR_FALCON_HWCFG 0x10a108 +#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 +#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 +#define NV_PPWR_FALCON_DMACTL 0x10a10c +#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 +#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 +#define NV_PPWR_FALCON_DMATRFBASE 0x10a110 +#define NV_PPWR_FALCON_DMATRFMOFFS 0x10a114 +#define NV_PPWR_FALCON_DMATRFCMD 0x10a118 +#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 +#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 +#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 +#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 +#define NV_PPWR_FALCON_DMATRFFBOFFS 0x10a11c +#define NV_PPWR_FALCON_EXTERRADDR 0x10a168 +#define NV_PPWR_FALCON_EXTERRSTAT 0x10a16c +#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 +#define NV_PPWR_FALCON_ICD_CMD 0x10a200 +#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 8 +#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 14 +#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 +#define NV_PPWR_FALCON_ICD_RDATA 0x10a20c +#define NV_PPWR_FALCON_IMEMC(i) (0x10a180+(i)*16) +#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_IMEMC_BLK 15:8 +#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_IMEMD(i) (0x10a184+(i)*16) +#define NV_PPWR_FALCON_IMEMT(i) (0x10a188+(i)*16) +#define NV_PPWR_FALCON_DMEMC(i) (0x10a1c0+(i)*8) +#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 +#define NV_PPWR_FALCON_DMEMC_BLK 15:8 +#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 +#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 +#define NV_PPWR_FALCON_DMEMD(i) (0x10a1c4+(i)*8) +#define NV_PPWR_PMU_NEW_INSTBLK 0x10a47c +#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0 +#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 2 +#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 +#define NV_PPWR_PMU_MUTEX_ID 0x10a488 +#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0xff +#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x10a48c +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0 +#define NV_PPWR_PMU_MUTEX(i) (0x10a580+(i)*4) +#define NV_PPWR_PMU_MUTEX__SIZE_1 16 +#define NV_PPWR_PMU_MUTEX_VALUE 7:0 +#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0 +#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x10a4a0+(i)*4) +#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 +#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x10a4b0+(i)*4) +#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 4 +#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 +#define NV_PPWR_PMU_MSGQ_HEAD 0x10a4c8 +#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 +#define NV_PPWR_PMU_MSGQ_TAIL 0x10a4cc +#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 +#define NV_PPWR_PMU_IDLE_MASK(i) (0x10a504+(i)*16) +#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 +#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 +#define NV_PPWR_PMU_IDLE_COUNT(i) (0x10a508+(i)*16) +#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 +#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 +#define NV_PPWR_PMU_IDLE_CTRL(i) (0x10a50c+(i)*16) +#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 2 +#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 3 +#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 +#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x10a9f0+(i)*8) +#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x10a9f4+(i)*8) +#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x10aa30+(i)*8) +#define NV_PPWR_PMU_DEBUG(i) (0x10a5c0+(i)*4) +#define NV_PPWR_PMU_DEBUG__SIZE_1 4 +#define NV_PPWR_PMU_MAILBOX(i) (0x10a5d0+(i)*4) +#define NV_PPWR_PMU_MAILBOX__SIZE_1 4 +#define NV_PPWR_PMU_BAR0_ADDR 0x10a7a0 +#define NV_PPWR_PMU_BAR0_DATA 0x10a7a4 +#define NV_PPWR_PMU_BAR0_CTL 0x10a7ac +#define NV_PPWR_PMU_BAR0_TIMEOUT 0x10a7a8 +#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x10a7b0 +#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x10a988 +#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x10a6c0+(i)*4) +#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x10a6e8+(i)*4) +#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x10a710+(i)*4) +#define NV_PPWR_PMU_PG_INTREN(i) (0x10a760+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG(i) (0x10a600+(i)*4) +#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 1 +#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0 +#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 1 + +#endif /* __nv_gk110b_pwr_pri_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_ram_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ram_hwref.h new file mode 100644 index 000000000..e29982b08 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_ram_hwref.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_ram_hwref_h__ +#define __nv_gk110b_ram_hwref_h__ + +#define NV_RAMIN_BASE_SHIFT 12 +#define NV_RAMIN_ALLOC_SIZE 0x1000 +#define NV_RAMIN_RAMFC (0x7f*32+31):(0*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (0x80*32+1):(0x80*32+0) +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0 +#define NV_RAMIN_PAGE_DIR_BASE_VOL (0x80*32+2):(0x80*32+2) +#define NV_RAMIN_PAGE_DIR_BASE_LO (0x80*32+31):(0x80*32+12) +#define NV_RAMIN_PAGE_DIR_BASE_HI (0x81*32+7):(0x81*32+0) +#define NV_RAMIN_ADR_LIMIT_LO (0x82*32+31):(0x82*32+12) +#define NV_RAMIN_ADR_LIMIT_HI (0x83*32+7):(0x83*32+0) +#define NV_RAMIN_ENGINE_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_ENGINE_CS_WFI 0 +#define NV_RAMIN_ENGINE_CS_FG 1 +#define NV_RAMIN_GR_CS (0x84*32+3):(0x84*32+3) +#define NV_RAMIN_GR_CS_WFI 0 +#define NV_RAMIN_GR_WFI_TARGET (0x84*32+1):(0x84*32+0) +#define NV_RAMIN_GR_WFI_MODE (0x84*32+2):(0x84*32+2) +#define NV_RAMIN_GR_WFI_MODE_PHYSICAL 0 +#define NV_RAMIN_GR_WFI_MODE_VIRTUAL 1 +#define NV_RAMIN_GR_WFI_PTR_LO (0x84*32+31):(0x84*32+12) +#define NV_RAMIN_GR_WFI_PTR_HI (0x85*32+7):(0x85*32+0) +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) +#define NV_RAMFC_USERD (2*32+31):(2*32+0) +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) +#define NV_RAMFC_SEMAPHOREA (14*32+31):(14*32+0) +#define NV_RAMFC_SEMAPHOREB (15*32+31):(15*32+0) +#define NV_RAMFC_SEMAPHOREC (16*32+31):(16*32+0) +#define NV_RAMFC_SEMAPHORED (17*32+31):(17*32+0) +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) +#define NV_RAMFC_PB_HEADER (0x21*32+31):(0x21*32+0) +#define NV_RAMFC_PB_COUNT (0x22*32+31):(0x22*32+0) +#define NV_RAMFC_SUBDEVICE (0x25*32+31):(0x25*32+0) +#define NV_RAMFC_FORMATS (0x27*32+31):(0x27*32+0) +#define NV_RAMFC_TARGET (0x2b*32+31):(0x2b*32+0) +#define NV_RAMFC_HCE_CTRL (0x39*32+31):(0x39*32+0) +#define NV_RAMFC_CHID (0x3a*32+31):(0x3a*32+0) +#define NV_RAMFC_CHID_ID 11:0 +#define NV_RAMFC_RUNLIST_TIMESLICE (0x3e*32+31):(0x3e*32+0) +#define NV_RAMFC_PB_TIMESLICE (0x3f*32+31):(0x3f*32+0) +#define NV_RAMFC_SIZE_VAL 0x200 +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) +#define NV_RAMUSERD_REF_THRESHOLD (20*32+31):(20*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET (22*32+31):(22*32+0) +#define NV_RAMUSERD_GP_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) +#define NV_RAMUSERD_GP_GET (0x22*32+31):(0x22*32+0) +#define NV_RAMUSERD_GP_PUT (0x23*32+31):(0x23*32+0) +#define NV_RAMUSERD_BASE_SHIFT 9 +#define NV_RAMUSERD_CHAN_SIZE 0x200 +#define NV_RAMRL_ENTRY_CHID 11:0 +#define NV_RAMRL_ENTRY_ID 11:0 +#define NV_RAMRL_ENTRY_TYPE 13:13 +#define NV_RAMRL_ENTRY_TYPE_CHID 0 +#define NV_RAMRL_ENTRY_TYPE_TSG 1 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE 17:14 +#define NV_RAMRL_ENTRY_TIMESLICE_SCALE_3 3 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT 25:18 +#define NV_RAMRL_ENTRY_TIMESLICE_TIMEOUT_128 0x80 +#define NV_RAMRL_ENTRY_TSG_LENGTH 31:26 +#define NV_RAMRL_ENTRY_SIZE 8 + +#endif /* __nv_gk110b_ram_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_therm_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_therm_hwref.h new file mode 100644 index 000000000..9b9551e68 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_therm_hwref.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_therm_hwref_h__ +#define __nv_gk110b_therm_hwref_h__ + +#define NV_THERM_USE_A 0x20798 +#define NV_THERM_WEIGHT_1 0x20024 +#define NV_THERM_CONFIG1 0x20050 +#define NV_THERM_CLK_SLOWDOWN_0(i) (0x20160+((i)*4)) +#define NV_THERM_CLK_SLOWDOWN_0_IDLE_FACTOR 21:16 +#define NV_THERM_GATE_CTRL(i) (0x20200+((i)*4)) +#define NV_THERM_GATE_CTRL_ENG_CLK 1:0 +#define NV_THERM_GATE_CTRL_ENG_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_ENG_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_CLK_STOP 2 +#define NV_THERM_GATE_CTRL_BLK_CLK 3:2 +#define NV_THERM_GATE_CTRL_BLK_CLK_RUN 0 +#define NV_THERM_GATE_CTRL_BLK_CLK_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR 5:4 +#define NV_THERM_GATE_CTRL_ENG_PWR_AUTO 1 +#define NV_THERM_GATE_CTRL_ENG_PWR_OFF 2 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP 12:8 +#define NV_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT 15:13 +#define NV_THERM_GATE_CTRL_ENG_DELAY_AFTER 23:20 +#define NV_THERM_FECS_IDLE_FILTER 0x20288 +#define NV_THERM_FECS_IDLE_FILTER_VALUE 31:0 +#define NV_THERM_HUBMMU_IDLE_FILTER 0x2028c +#define NV_THERM_HUBMMU_IDLE_FILTER_VALUE 31:0 + +#endif /* __nv_gk110b_therm_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_timer_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_timer_hwref.h new file mode 100644 index 000000000..d6a465150 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_timer_hwref.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_timer_hwref_h__ +#define __nv_gk110b_timer_hwref_h__ + +#define NV_PTIMER_PRI_TIMEOUT 0x9080 +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x9084 +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x9088 +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x908c + +#endif /* __nv_gk110b_timer_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_top_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_top_hwref.h new file mode 100644 index 000000000..d4df634d3 --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_top_hwref.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_top_hwref_h__ +#define __nv_gk110b_top_hwref_h__ + +#define NV_PTOP_SCAL_NUM_GPCS 0x22430 +#define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x22434 +#define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 +#define NV_PTOP_SCAL_NUM_FBPS 0x22438 +#define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 +#define NV_PTOP_FS_STATUS 0x22500 +#define NV_PTOP_FS_STATUS_FBP 0x22548 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER 15:0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_ENABLE 0 +#define NV_PTOP_FS_STATUS_FBP_CLUSTER_DISABLE 1 +#define NV_PTOP_DEVICE_INFO(i) (0x22700+(i)*4) +#define NV_PTOP_DEVICE_INFO__SIZE_1 0x40 +#define NV_PTOP_DEVICE_INFO_CHAIN 31:31 +#define NV_PTOP_DEVICE_INFO_CHAIN_ENABLE 1 +#define NV_PTOP_DEVICE_INFO_ENGINE_ENUM 29:26 +#define NV_PTOP_DEVICE_INFO_RUNLIST_ENUM 24:21 +#define NV_PTOP_DEVICE_INFO_INTR_ENUM 19:15 +#define NV_PTOP_DEVICE_INFO_RESET_ENUM 13:9 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM 30:2 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS 0 +#define NV_PTOP_DEVICE_INFO_TYPE_ENUM_COPY0 1 +#define NV_PTOP_DEVICE_INFO_ENTRY 1:0 +#define NV_PTOP_DEVICE_INFO_ENTRY_NOT_VALID 0 +#define NV_PTOP_DEVICE_INFO_ENTRY_ENUM 2 + +#endif /* __nv_gk110b_top_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_addendum_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_addendum_hwref.h new file mode 100644 index 000000000..95cc09dfd --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_addendum_hwref.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_trim_addendum_hwref_h__ +#define __nv_gk110b_trim_addendum_hwref_h__ + +#define NV_PTRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG + +#endif /* __nv_gk110b_trim_addendum_hwref_h__ */ diff --git a/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_hwref.h b/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_hwref.h new file mode 100644 index 000000000..25dd3e60a --- /dev/null +++ b/drm/nouveau/include/nvkm/hwref/gk110b/nv_trim_hwref.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __nv_gk110b_trim_hwref_h__ +#define __nv_gk110b_trim_hwref_h__ + +#define NV_PTRIM_SYS_GPCPLL_CFG 0x137000 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 +#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET 4:4 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON 0 +#define NV_PTRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF 1 +#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 +#define NV_PTRIM_SYS_GPCPLL_COEFF 0x137004 +#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 +#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 +#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 +#define NV_PTRIM_SYS_GPCPLL_CFG2 0x13700c +#define NV_PTRIM_SYS_GPCPLL_CFG2_PLL_STEPA 31:24 +#define NV_PTRIM_SYS_GPCPLL_CFG3 0x137018 +#define NV_PTRIM_SYS_GPCPLL_CFG3_PLL_STEPB 23:16 +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x13701c +#define NV_PTRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL 22:22 +#define NV_PTRIM_SYS_SEL_VCO 0x137100 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT 0:0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS 0 +#define NV_PTRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO 1 +#define NV_PTRIM_SYS_GPC2CLK_OUT 0x137250 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV 5:0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31 0x3c +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV 13:8 +#define NV_PTRIM_SYS_GPC2CLK_OUT_VCODIV_BY1 0 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14 31:31 +#define NV_PTRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x137340 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL 0:0 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_BYPASSCLK 1 +#define NV_PTRIM_SYS_BYPASSCTRL_SYS_GPCPLL_VCO 0 +#define NV_PTRIM_GPC_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP 31:31 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x134124+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS 13:0 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN 16:16 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE 20:20 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 1 +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x134128+(i)*0x200) +#define NV_PTRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE 19:0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG 0x1328a0 +#define NV_PTRIM_GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED 24:24 + +#endif /* __nv_gk110b_trim_hwref_h__ */ |