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| author | Alexandre Courbot <acourbot@nvidia.com> | 2016-04-11 16:57:43 +0900 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2016-07-13 15:25:04 +0900 |
| commit | a3b5043d1f50e3d572b5fe3cca7c96bc1a3f57c3 (patch) | |
| tree | a23d9fb34b6ee8e56ad0a8243bd0755a5bc61de7 /drm/nouveau/nvkm/engine/device/pci.c | |
| parent | c6428e4fd8f0f894b2f0bc1ac5baa95f241a497b (diff) | |
| download | nouveau-a3b5043d1f50e3d572b5fe3cca7c96bc1a3f57c3.tar.gz | |
bus: remove cpu_coherent flagstaging/bo
This flag's only remaining function is to ignore the uncached flag for
BOs on coherent architectures.
However the reason for allocating an object uncache on a non-coherent
architecture (namely because the cost of doing explicit flushes/
invalidations is higher than the benefit of caching the data because
accesses are few and far between) should also apply on architectures for
which coherency is maintained implicitly. Thus allocate coherent objects
as uncached on all architectures.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Diffstat (limited to 'drm/nouveau/nvkm/engine/device/pci.c')
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/pci.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drm/nouveau/nvkm/engine/device/pci.c b/drm/nouveau/nvkm/engine/device/pci.c index 62ad0300c..b1b693219 100644 --- a/drm/nouveau/nvkm/engine/device/pci.c +++ b/drm/nouveau/nvkm/engine/device/pci.c @@ -1614,7 +1614,6 @@ nvkm_device_pci_func = { .fini = nvkm_device_pci_fini, .resource_addr = nvkm_device_pci_resource_addr, .resource_size = nvkm_device_pci_resource_size, - .cpu_coherent = !IS_ENABLED(CONFIG_ARM), }; int |