diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2015-08-20 14:54:19 +1000 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2015-08-28 12:37:41 +1000 |
commit | bef1fab512565193b40cd5a8356b4007ffa8c501 (patch) | |
tree | 1a1de76054c0fd55efaf5d0c7b090b83548e8044 /drm/nouveau/nvkm/engine/gr/nv2a.c | |
parent | e79f192fe7c88465e9cbcae56971858791019c0b (diff) | |
download | nouveau-bef1fab512565193b40cd5a8356b4007ffa8c501.tar.gz |
gr: convert user classes to new-style nvkm_object
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drm/nouveau/nvkm/engine/gr/nv2a.c')
-rw-r--r-- | drm/nouveau/nvkm/engine/gr/nv2a.c | 144 |
1 files changed, 82 insertions, 62 deletions
diff --git a/drm/nouveau/nvkm/engine/gr/nv2a.c b/drm/nouveau/nvkm/engine/gr/nv2a.c index c5d8cd6d6..2fabdc586 100644 --- a/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -8,90 +8,110 @@ * PGRAPH context ******************************************************************************/ +static const struct nvkm_object_func +nv2a_gr_chan = { + .dtor = nv20_gr_chan_dtor, + .init = nv20_gr_chan_init, + .fini = nv20_gr_chan_fini, +}; + static int -nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv2a_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { + struct nv20_gr *gr = nv20_gr(base); struct nv20_gr_chan *chan; - struct nvkm_gpuobj *image; int ret, i; - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv2a_gr_chan, oclass, &chan->object); + chan->gr = gr; + chan->chid = fifoch->chid; + *pobject = &chan->object; + + ret = nvkm_memory_new(gr->base.engine.subdev.device, + NVKM_MEM_TARGET_INST, 0x36b0, 16, true, + &chan->inst); if (ret) return ret; - chan->chid = nvkm_fifo_chan(parent)->chid; - image = &chan->base.base.gpuobj; - - nvkm_kmap(image); - nvkm_wo32(image, 0x0000, 0x00000001 | (chan->chid << 24)); - nvkm_wo32(image, 0x033c, 0xffff0000); - nvkm_wo32(image, 0x03a0, 0x0fff0000); - nvkm_wo32(image, 0x03a4, 0x0fff0000); - nvkm_wo32(image, 0x047c, 0x00000101); - nvkm_wo32(image, 0x0490, 0x00000111); - nvkm_wo32(image, 0x04a8, 0x44400000); + nvkm_kmap(chan->inst); + nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(chan->inst, 0x033c, 0xffff0000); + nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); + nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); + nvkm_wo32(chan->inst, 0x047c, 0x00000101); + nvkm_wo32(chan->inst, 0x0490, 0x00000111); + nvkm_wo32(chan->inst, 0x04a8, 0x44400000); for (i = 0x04d4; i <= 0x04e0; i += 4) - nvkm_wo32(image, i, 0x00030303); + nvkm_wo32(chan->inst, i, 0x00030303); for (i = 0x04f4; i <= 0x0500; i += 4) - nvkm_wo32(image, i, 0x00080000); + nvkm_wo32(chan->inst, i, 0x00080000); for (i = 0x050c; i <= 0x0518; i += 4) - nvkm_wo32(image, i, 0x01012000); + nvkm_wo32(chan->inst, i, 0x01012000); for (i = 0x051c; i <= 0x0528; i += 4) - nvkm_wo32(image, i, 0x000105b8); + nvkm_wo32(chan->inst, i, 0x000105b8); for (i = 0x052c; i <= 0x0538; i += 4) - nvkm_wo32(image, i, 0x00080008); + nvkm_wo32(chan->inst, i, 0x00080008); for (i = 0x055c; i <= 0x0598; i += 4) - nvkm_wo32(image, i, 0x07ff0000); - nvkm_wo32(image, 0x05a4, 0x4b7fffff); - nvkm_wo32(image, 0x05fc, 0x00000001); - nvkm_wo32(image, 0x0604, 0x00004000); - nvkm_wo32(image, 0x0610, 0x00000001); - nvkm_wo32(image, 0x0618, 0x00040000); - nvkm_wo32(image, 0x061c, 0x00010000); + nvkm_wo32(chan->inst, i, 0x07ff0000); + nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff); + nvkm_wo32(chan->inst, 0x05fc, 0x00000001); + nvkm_wo32(chan->inst, 0x0604, 0x00004000); + nvkm_wo32(chan->inst, 0x0610, 0x00000001); + nvkm_wo32(chan->inst, 0x0618, 0x00040000); + nvkm_wo32(chan->inst, 0x061c, 0x00010000); for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ - nvkm_wo32(image, (i + 0), 0x10700ff9); - nvkm_wo32(image, (i + 4), 0x0436086c); - nvkm_wo32(image, (i + 8), 0x000c001b); + nvkm_wo32(chan->inst, (i + 0), 0x10700ff9); + nvkm_wo32(chan->inst, (i + 4), 0x0436086c); + nvkm_wo32(chan->inst, (i + 8), 0x000c001b); } - nvkm_wo32(image, 0x269c, 0x3f800000); - nvkm_wo32(image, 0x26b0, 0x3f800000); - nvkm_wo32(image, 0x26dc, 0x40000000); - nvkm_wo32(image, 0x26e0, 0x3f800000); - nvkm_wo32(image, 0x26e4, 0x3f000000); - nvkm_wo32(image, 0x26ec, 0x40000000); - nvkm_wo32(image, 0x26f0, 0x3f800000); - nvkm_wo32(image, 0x26f8, 0xbf800000); - nvkm_wo32(image, 0x2700, 0xbf800000); - nvkm_wo32(image, 0x3024, 0x000fe000); - nvkm_wo32(image, 0x30a0, 0x000003f8); - nvkm_wo32(image, 0x33fc, 0x002fe000); + nvkm_wo32(chan->inst, 0x269c, 0x3f800000); + nvkm_wo32(chan->inst, 0x26b0, 0x3f800000); + nvkm_wo32(chan->inst, 0x26dc, 0x40000000); + nvkm_wo32(chan->inst, 0x26e0, 0x3f800000); + nvkm_wo32(chan->inst, 0x26e4, 0x3f000000); + nvkm_wo32(chan->inst, 0x26ec, 0x40000000); + nvkm_wo32(chan->inst, 0x26f0, 0x3f800000); + nvkm_wo32(chan->inst, 0x26f8, 0xbf800000); + nvkm_wo32(chan->inst, 0x2700, 0xbf800000); + nvkm_wo32(chan->inst, 0x3024, 0x000fe000); + nvkm_wo32(chan->inst, 0x30a0, 0x000003f8); + nvkm_wo32(chan->inst, 0x33fc, 0x002fe000); for (i = 0x341c; i <= 0x3438; i += 4) - nvkm_wo32(image, i, 0x001c527c); - nvkm_done(image); + nvkm_wo32(chan->inst, i, 0x001c527c); + nvkm_done(chan->inst); return 0; } -static struct nvkm_oclass -nv2a_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x2a), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv2a_gr_context_ctor, - .dtor = _nvkm_gr_context_dtor, - .init = nv20_gr_context_init, - .fini = nv20_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, -}; - /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct nvkm_gr_func +nv2a_gr = { + .chan_new = nv2a_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ + { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ + { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */ + {} + } +}; + static int nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -106,6 +126,8 @@ nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + gr->base.func = &nv2a_gr; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, &gr->ctxtab); if (ret) @@ -113,8 +135,6 @@ nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->cclass = &nv2a_gr_cclass; - nv_engine(gr)->sclass = nv25_gr_sclass; nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } |