Share gk20a pll

3 files changed, 24 insertions, 45 deletions

diff --git a/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drm/nouveau/nvkm/subdev/clk/gk20a.c
index 3383810eb..43c42c696 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk20a.c
+++ b/drm/nouveau/nvkm/subdev/clk/gk20a.c
@@ -50,12 +50,6 @@ static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
 	.min_pl = 1, .max_pl = 32,
 };
 
-struct gk20a_pll {
-	u32 m;
-	u32 n;
-	u32 pl;
-};
-
 struct gk20a_clk {
 	struct nvkm_clk base;
 	const struct gk20a_clk_pllg_params *params;
@@ -63,10 +57,10 @@ struct gk20a_clk {
 	u32 parent_rate;
 };
 
-static void
-gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
+void
+gk20a_pllg_read_mnp(struct nvkm_clk *clk, struct gk20a_pll *pll)
 {
-	struct nvkm_device *device = clk->base.subdev.device;
+	struct nvkm_device *device = clk->subdev.device;
 	u32 val;
 
 	val = nvkm_rd32(device, GPCPLL_COEFF);
@@ -286,22 +280,22 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
 	struct nvkm_subdev *subdev = &clk->base.subdev;
 	struct nvkm_device *device = subdev->device;
 	u32 val, cfg;
-	u32 m_old, pl_old, n_lo;
+	struct gk20a_pll pll;
+	u32 n_lo;
 
 	/* get old coefficients */
+	gk20a_pllg_read_mnp(&clk->base, &pll);
 	val = nvkm_rd32(device, GPCPLL_COEFF);
-	m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
-	pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
 
 	/* do NDIV slide if there is no change in M and PL */
 	cfg = nvkm_rd32(device, GPCPLL_CFG);
-	if (allow_slide && clk->pll.m == m_old && clk->pll.pl == pl_old &&
+	if (allow_slide && clk->pll.m == pll.m && clk->pll.pl == pll.pl &&
 	    (cfg & GPCPLL_CFG_ENABLE)) {
 		return gk20a_pllg_slide(clk, clk->pll.n);
 	}
 
 	/* slide down to NDIV_LO */
-	n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco,
+	n_lo = DIV_ROUND_UP(pll.m * clk->params->min_vco,
 			    clk->parent_rate / KHZ);
 	if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) {
 		int ret = gk20a_pllg_slide(clk, n_lo);
@@ -511,7 +505,7 @@ gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
 	case nv_clk_src_crystal:
 		return device->crystal;
 	case nv_clk_src_gpc:
-		gk20a_pllg_read_mnp(clk, &clk->pll);
+		gk20a_pllg_read_mnp(&clk->base, &clk->pll);
 		return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV;
 	default:
 		nvkm_error(subdev, "invalid clock source %d\n", src);
diff --git a/drm/nouveau/nvkm/subdev/clk/gk20a.h b/drm/nouveau/nvkm/subdev/clk/gk20a.h
index 0aa914417..f732d2cc9 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk20a.h
+++ b/drm/nouveau/nvkm/subdev/clk/gk20a.h
@@ -103,4 +103,12 @@ struct gk20a_clk_pllg_params {
 	u32 min_pl, max_pl;
 };
 
+struct gk20a_pll {
+	u32 m;
+	u32 n;
+	u32 pl;
+};
+
+void gk20a_pllg_read_mnp(struct nvkm_clk *clk, struct gk20a_pll *pll);
+
 #endif
diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c
index 90803bd79..bd52021df 100644
--- a/drm/nouveau/nvkm/subdev/clk/gm20b.c
+++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c
@@ -113,12 +113,6 @@ struct gm20b_pllg_fused_params {
 	int uvdet_slope, uvdet_offs;
 };
 
-struct gm20b_pll {
-	u32 m;
-	u32 n;
-	u32 pl;
-};
-
 struct gm20b_na_dvfs {
 	u32 n_int;
 	u32 sdm_din;
@@ -143,7 +137,7 @@ static const struct gm20b_pllg_na_params gm20b_pllg_na_params = {
 };
 
 struct gm20b_gpcpll {
-	struct gm20b_pll pll;
+	struct gk20a_pll pll;
 	struct gm20b_na_dvfs dvfs;
 	u32 rate;	/* gpc2clk */
 };
@@ -176,30 +170,13 @@ static u32 gm20b_pllg_get_interim_pldiv(u32 old, u32 new)
 }
 
 static void
-gm20b_gpcpll_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll)
-{
-	struct nvkm_device *device = clk->base.subdev.device;
-	u32 val;
-
-	if (!pll) {
-		WARN(1, "%s() - invalid PLL\n", __func__);
-		return;
-	}
-
-	val = nvkm_rd32(device, GPCPLL_COEFF);
-	pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
-	pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
-	pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
-}
-
-static void
 gm20b_pllg_read_mnp(struct gm20b_clk *clk)
 {
-	gm20b_gpcpll_read_mnp(clk, &clk->gpcpll.pll);
+	gk20a_pllg_read_mnp(&clk->base, &clk->gpcpll.pll);
 }
 
 static u32
-gm20b_pllg_calc_rate(u32 ref_rate, struct gm20b_pll *pll)
+gm20b_pllg_calc_rate(u32 ref_rate, struct gk20a_pll *pll)
 {
 	u32 rate;
 	u32 divider;
@@ -501,7 +478,7 @@ gm20b_pllg_slide(struct gm20b_clk *clk, struct gm20b_gpcpll *gpcpll)
 {
 	struct nvkm_subdev *subdev = &clk->base.subdev;
 	struct nvkm_device *device = subdev->device;
-	struct gm20b_pll pll = gpcpll->pll;
+	struct gk20a_pll pll = gpcpll->pll;
 	u32 val;
 	u32 nold, sdmold;
 	int ramp_timeout;
@@ -718,7 +695,7 @@ _gm20b_pllg_program_mnp(struct gm20b_clk *clk,
 	int ret;
 
 	/* get old coefficients */
-	gm20b_gpcpll_read_mnp(clk, &gpll.pll);
+	gk20a_pllg_read_mnp(&clk->base, &gpll.pll);
 
 	gpll.dvfs = gpcpll->dvfs;
 
@@ -1019,7 +996,7 @@ gm20b_pllg_disable(struct gm20b_clk *clk)
 	if (val & GPCPLL_CFG_ENABLE) {
 		struct gm20b_gpcpll gpcpll = clk->gpcpll;
 
-		gm20b_gpcpll_read_mnp(clk, &gpcpll.pll);
+		gk20a_pllg_read_mnp(&clk->base, &gpcpll.pll);
 		gpcpll.pll.n = DIV_ROUND_UP(gpcpll.pll.m * clk->params->min_vco,
 				                                clk->parent_rate / KHZ);
 		if (clk->napll_enabled)
@@ -1191,7 +1168,7 @@ gm20b_clk_init(struct nvkm_clk *base)
 	struct nvkm_subdev *subdev = &clk->base.subdev;
 	struct nvkm_device *device = subdev->device;
 	struct gm20b_gpcpll *gpcpll = &clk->gpcpll;
-	struct gm20b_pll *pll = &gpcpll->pll;
+	struct gk20a_pll *pll = &gpcpll->pll;
 	u32 val;
 	int ret;