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path: root/drm/nouveau/nvkm/engine/device/base.c
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Diffstat (limited to 'drm/nouveau/nvkm/engine/device/base.c')
-rw-r--r--drm/nouveau/nvkm/engine/device/base.c138
1 files changed, 69 insertions, 69 deletions
diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c
index 62395ab74..3cf15d46f 100644
--- a/drm/nouveau/nvkm/engine/device/base.c
+++ b/drm/nouveau/nvkm/engine/device/base.c
@@ -89,7 +89,7 @@ nv4_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv04_fifo_new,
-// .gr = nv04_gr_new,
+ .gr = nv04_gr_new,
// .sw = nv04_sw_new,
};
@@ -109,7 +109,7 @@ nv5_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv04_fifo_new,
-// .gr = nv04_gr_new,
+ .gr = nv04_gr_new,
// .sw = nv04_sw_new,
};
@@ -129,7 +129,7 @@ nv10_chipset = {
.timer = nv04_timer_new,
.disp = nv04_disp_new,
.dma = nv04_dma_new,
-// .gr = nv10_gr_new,
+ .gr = nv10_gr_new,
};
static const struct nvkm_device_chip
@@ -149,7 +149,7 @@ nv11_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv10_fifo_new,
-// .gr = nv10_gr_new,
+ .gr = nv15_gr_new,
// .sw = nv10_sw_new,
};
@@ -170,7 +170,7 @@ nv15_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv10_fifo_new,
-// .gr = nv10_gr_new,
+ .gr = nv15_gr_new,
// .sw = nv10_sw_new,
};
@@ -191,7 +191,7 @@ nv17_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv10_gr_new,
+ .gr = nv17_gr_new,
// .sw = nv10_sw_new,
};
@@ -212,7 +212,7 @@ nv18_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv10_gr_new,
+ .gr = nv17_gr_new,
// .sw = nv10_sw_new,
};
@@ -233,7 +233,7 @@ nv1a_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv10_fifo_new,
-// .gr = nv10_gr_new,
+ .gr = nv15_gr_new,
// .sw = nv10_sw_new,
};
@@ -254,7 +254,7 @@ nv1f_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv10_gr_new,
+ .gr = nv17_gr_new,
// .sw = nv10_sw_new,
};
@@ -275,7 +275,7 @@ nv20_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv20_gr_new,
+ .gr = nv20_gr_new,
// .sw = nv10_sw_new,
};
@@ -296,7 +296,7 @@ nv25_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv25_gr_new,
+ .gr = nv25_gr_new,
// .sw = nv10_sw_new,
};
@@ -317,7 +317,7 @@ nv28_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv25_gr_new,
+ .gr = nv25_gr_new,
// .sw = nv10_sw_new,
};
@@ -338,7 +338,7 @@ nv2a_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv2a_gr_new,
+ .gr = nv2a_gr_new,
// .sw = nv10_sw_new,
};
@@ -359,7 +359,7 @@ nv30_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv30_gr_new,
+ .gr = nv30_gr_new,
// .sw = nv10_sw_new,
};
@@ -380,7 +380,7 @@ nv31_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv30_gr_new,
+ .gr = nv30_gr_new,
// .mpeg = nv31_mpeg_new,
// .sw = nv10_sw_new,
};
@@ -402,7 +402,7 @@ nv34_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv34_gr_new,
+ .gr = nv34_gr_new,
// .mpeg = nv31_mpeg_new,
// .sw = nv10_sw_new,
};
@@ -424,7 +424,7 @@ nv35_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv35_gr_new,
+ .gr = nv35_gr_new,
// .sw = nv10_sw_new,
};
@@ -445,7 +445,7 @@ nv36_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv17_fifo_new,
-// .gr = nv35_gr_new,
+ .gr = nv35_gr_new,
// .mpeg = nv31_mpeg_new,
// .sw = nv10_sw_new,
};
@@ -469,7 +469,7 @@ nv40_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -494,7 +494,7 @@ nv41_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -519,7 +519,7 @@ nv42_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -544,7 +544,7 @@ nv43_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -569,7 +569,7 @@ nv44_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -594,7 +594,7 @@ nv45_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -619,7 +619,7 @@ nv46_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -644,7 +644,7 @@ nv47_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -669,7 +669,7 @@ nv49_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -694,7 +694,7 @@ nv4a_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -719,7 +719,7 @@ nv4b_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -744,7 +744,7 @@ nv4c_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -769,7 +769,7 @@ nv4e_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -797,7 +797,7 @@ nv50_chipset = {
.disp = nv50_disp_new,
.dma = nv50_dma_new,
.fifo = nv50_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = nv50_gr_new,
// .mpeg = nv50_mpeg_new,
// .pm = nv50_pm_new,
// .sw = nv50_sw_new,
@@ -822,7 +822,7 @@ nv63_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -847,7 +847,7 @@ nv67_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -872,7 +872,7 @@ nv68_chipset = {
.disp = nv04_disp_new,
.dma = nv04_dma_new,
.fifo = nv40_fifo_new,
-// .gr = nv40_gr_new,
+ .gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
@@ -902,7 +902,7 @@ nv84_chipset = {
.disp = g84_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
@@ -933,7 +933,7 @@ nv86_chipset = {
.disp = g84_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
@@ -964,7 +964,7 @@ nv92_chipset = {
.disp = g84_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
@@ -995,7 +995,7 @@ nv94_chipset = {
.disp = g94_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
@@ -1024,7 +1024,7 @@ nv96_chipset = {
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
// .sw = nv50_sw_new,
-// .gr = nv50_gr_new,
+ .gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
.vp = g84_vp_new,
.cipher = g84_cipher_new,
@@ -1055,7 +1055,7 @@ nv98_chipset = {
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
// .sw = nv50_sw_new,
-// .gr = nv50_gr_new,
+ .gr = g84_gr_new,
.mspdec = g98_mspdec_new,
.sec = g98_sec_new,
.msvld = g98_msvld_new,
@@ -1088,7 +1088,7 @@ nva0_chipset = {
.disp = gt200_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = gt200_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = gt200_pm_new,
// .sw = nv50_sw_new,
@@ -1119,7 +1119,7 @@ nva3_chipset = {
.disp = gt215_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = gt215_gr_new,
// .mpeg = g84_mpeg_new,
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
@@ -1152,7 +1152,7 @@ nva5_chipset = {
.disp = gt215_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = gt215_gr_new,
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
@@ -1184,7 +1184,7 @@ nva8_chipset = {
.disp = gt215_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = gt215_gr_new,
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
@@ -1214,7 +1214,7 @@ nvaa_chipset = {
.disp = g94_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = gt200_gr_new,
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
@@ -1245,7 +1245,7 @@ nvac_chipset = {
.disp = g94_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = mcp79_gr_new,
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
@@ -1278,7 +1278,7 @@ nvaf_chipset = {
.disp = gt215_disp_new,
.dma = nv50_dma_new,
.fifo = g84_fifo_new,
-// .gr = nv50_gr_new,
+ .gr = mcp89_gr_new,
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = mcp89_msvld_new,
@@ -1313,7 +1313,7 @@ nvc0_chipset = {
.disp = gt215_disp_new,
.dma = gf100_dma_new,
.fifo = gf100_fifo_new,
-// .gr = gf100_gr_new,
+ .gr = gf100_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@@ -1347,7 +1347,7 @@ nvc1_chipset = {
.disp = gt215_disp_new,
.dma = gf100_dma_new,
.fifo = gf100_fifo_new,
-// .gr = gf108_gr_new,
+ .gr = gf108_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@@ -1381,7 +1381,7 @@ nvc3_chipset = {
.disp = gt215_disp_new,
.dma = gf100_dma_new,
.fifo = gf100_fifo_new,
-// .gr = gf104_gr_new,
+ .gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@@ -1416,7 +1416,7 @@ nvc4_chipset = {
.disp = gt215_disp_new,
.dma = gf100_dma_new,
.fifo = gf100_fifo_new,
-// .gr = gf104_gr_new,
+ .gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@@ -1451,7 +1451,7 @@ nvc8_chipset = {
.disp = gt215_disp_new,
.dma = gf100_dma_new,
.fifo = gf100_fifo_new,
-// .gr = gf110_gr_new,
+ .gr = gf110_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@@ -1486,7 +1486,7 @@ nvce_chipset = {
.disp = gt215_disp_new,
.dma = gf100_dma_new,
.fifo = gf100_fifo_new,
-// .gr = gf104_gr_new,
+ .gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@@ -1520,7 +1520,7 @@ nvcf_chipset = {
.disp = gt215_disp_new,
.dma = gf100_dma_new,
.fifo = gf100_fifo_new,
-// .gr = gf104_gr_new,
+ .gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@@ -1552,7 +1552,7 @@ nvd7_chipset = {
.disp = gf119_disp_new,
.dma = gf119_dma_new,
.fifo = gf100_fifo_new,
-// .gr = gf117_gr_new,
+ .gr = gf117_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@@ -1586,7 +1586,7 @@ nvd9_chipset = {
.disp = gf119_disp_new,
.dma = gf119_dma_new,
.fifo = gf100_fifo_new,
-// .gr = gf119_gr_new,
+ .gr = gf119_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@@ -1622,7 +1622,7 @@ nve4_chipset = {
.disp = gk104_disp_new,
.dma = gf119_dma_new,
.fifo = gk104_fifo_new,
-// .gr = gk104_gr_new,
+ .gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@@ -1658,7 +1658,7 @@ nve6_chipset = {
.disp = gk104_disp_new,
.dma = gf119_dma_new,
.fifo = gk104_fifo_new,
-// .gr = gk104_gr_new,
+ .gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@@ -1694,7 +1694,7 @@ nve7_chipset = {
.disp = gk104_disp_new,
.dma = gf119_dma_new,
.fifo = gk104_fifo_new,
-// .gr = gk104_gr_new,
+ .gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@@ -1721,7 +1721,7 @@ nvea_chipset = {
.ce[2] = gk104_ce_new,
.dma = gf119_dma_new,
.fifo = gk20a_fifo_new,
-// .gr = gk20a_gr_new,
+ .gr = gk20a_gr_new,
// .pm = gk104_pm_new,
// .sw = gf100_sw_new,
};
@@ -1754,7 +1754,7 @@ nvf0_chipset = {
.disp = gk110_disp_new,
.dma = gf119_dma_new,
.fifo = gk104_fifo_new,
-// .gr = gk110_gr_new,
+ .gr = gk110_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@@ -1790,7 +1790,7 @@ nvf1_chipset = {
.disp = gk110_disp_new,
.dma = gf119_dma_new,
.fifo = gk104_fifo_new,
-// .gr = gk110b_gr_new,
+ .gr = gk110b_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@@ -1826,7 +1826,7 @@ nv106_chipset = {
.disp = gk110_disp_new,
.dma = gf119_dma_new,
.fifo = gk208_fifo_new,
-// .gr = gk208_gr_new,
+ .gr = gk208_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@@ -1861,7 +1861,7 @@ nv108_chipset = {
.disp = gk110_disp_new,
.dma = gf119_dma_new,
.fifo = gk208_fifo_new,
-// .gr = gk208_gr_new,
+ .gr = gk208_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@@ -1894,7 +1894,7 @@ nv117_chipset = {
.disp = gm107_disp_new,
.dma = gf119_dma_new,
.fifo = gk208_fifo_new,
-// .gr = gm107_gr_new,
+ .gr = gm107_gr_new,
// .sw = gf100_sw_new,
};
@@ -1923,7 +1923,7 @@ nv124_chipset = {
.disp = gm204_disp_new,
.dma = gf119_dma_new,
.fifo = gm204_fifo_new,
-// .gr = gm204_gr_new,
+ .gr = gm204_gr_new,
// .sw = gf100_sw_new,
};
@@ -1952,7 +1952,7 @@ nv126_chipset = {
.disp = gm204_disp_new,
.dma = gf119_dma_new,
.fifo = gm204_fifo_new,
-// .gr = gm206_gr_new,
+ .gr = gm206_gr_new,
// .sw = gf100_sw_new,
};
@@ -1973,7 +1973,7 @@ nv12b_chipset = {
.ce[2] = gm204_ce_new,
.dma = gf119_dma_new,
.fifo = gm20b_fifo_new,
-// .gr = gm20b_gr_new,
+ .gr = gm20b_gr_new,
// .sw = gf100_sw_new,
};
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