diff options
Diffstat (limited to 'drm/nouveau/nvkm/engine')
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/base.c | 140 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/gf100.c | 9 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/gk104.c | 8 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/gm100.c | 5 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv04.c | 2 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv10.c | 8 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv20.c | 4 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv30.c | 5 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv40.c | 16 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/device/nv50.c | 14 | ||||
| -rw-r--r-- | drm/nouveau/nvkm/engine/dma/usernv04.c | 4 |
11 files changed, 72 insertions, 143 deletions
diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 96ac8804c..7da5dc44b 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -84,7 +84,7 @@ nv4_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -104,7 +104,7 @@ nv5_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -125,7 +125,7 @@ nv10_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -144,7 +144,7 @@ nv11_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -165,7 +165,7 @@ nv15_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -186,7 +186,7 @@ nv17_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -207,7 +207,7 @@ nv18_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -228,7 +228,7 @@ nv1a_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -249,7 +249,7 @@ nv1f_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -270,7 +270,7 @@ nv20_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -291,7 +291,7 @@ nv25_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -312,7 +312,7 @@ nv28_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -333,7 +333,7 @@ nv2a_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -354,7 +354,7 @@ nv30_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -375,7 +375,7 @@ nv31_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -397,7 +397,7 @@ nv34_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -419,7 +419,7 @@ nv35_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -440,7 +440,7 @@ nv36_chipset = { .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -462,7 +462,7 @@ nv40_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv40_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -487,7 +487,7 @@ nv41_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv40_mc_new, -// .mmu = nv41_mmu_new, + .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -512,7 +512,7 @@ nv42_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv40_mc_new, -// .mmu = nv41_mmu_new, + .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -537,7 +537,7 @@ nv43_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv40_mc_new, -// .mmu = nv41_mmu_new, + .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -562,7 +562,7 @@ nv44_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv44_mc_new, -// .mmu = nv44_mmu_new, + .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -587,7 +587,7 @@ nv45_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv40_mc_new, -// .mmu = nv04_mmu_new, + .mmu = nv04_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -612,7 +612,7 @@ nv46_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv44_mc_new, -// .mmu = nv44_mmu_new, + .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -637,7 +637,7 @@ nv47_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv40_mc_new, -// .mmu = nv41_mmu_new, + .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -662,7 +662,7 @@ nv49_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv40_mc_new, -// .mmu = nv41_mmu_new, + .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -687,7 +687,7 @@ nv4a_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv44_mc_new, -// .mmu = nv44_mmu_new, + .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -712,7 +712,7 @@ nv4b_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv40_mc_new, -// .mmu = nv41_mmu_new, + .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -737,7 +737,7 @@ nv4c_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv4c_mc_new, -// .mmu = nv44_mmu_new, + .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -762,7 +762,7 @@ nv4e_chipset = { .i2c = nv4e_i2c_new, .imem = nv40_instmem_new, .mc = nv4c_mc_new, -// .mmu = nv44_mmu_new, + .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -789,7 +789,7 @@ nv50_chipset = { .i2c = nv50_i2c_new, .imem = nv50_instmem_new, .mc = nv50_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = nv50_therm_new, // .timer = nv04_timer_new, @@ -815,7 +815,7 @@ nv63_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv4c_mc_new, -// .mmu = nv44_mmu_new, + .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -840,7 +840,7 @@ nv67_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv4c_mc_new, -// .mmu = nv44_mmu_new, + .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -865,7 +865,7 @@ nv68_chipset = { .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv4c_mc_new, -// .mmu = nv44_mmu_new, + .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -892,7 +892,7 @@ nv84_chipset = { .i2c = nv50_i2c_new, .imem = nv50_instmem_new, .mc = nv50_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, // .timer = nv04_timer_new, @@ -923,7 +923,7 @@ nv86_chipset = { .i2c = nv50_i2c_new, .imem = nv50_instmem_new, .mc = nv50_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, // .timer = nv04_timer_new, @@ -954,7 +954,7 @@ nv92_chipset = { .i2c = nv50_i2c_new, .imem = nv50_instmem_new, .mc = nv50_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, // .timer = nv04_timer_new, @@ -985,7 +985,7 @@ nv94_chipset = { .i2c = g94_i2c_new, .imem = nv50_instmem_new, .mc = g94_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, // .timer = nv04_timer_new, @@ -1018,7 +1018,7 @@ nv96_chipset = { // .timer = nv04_timer_new, .fb = g84_fb_new, .imem = nv50_instmem_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, .bar = g84_bar_new, // .volt = nv40_volt_new, // .dma = nv50_dma_new, @@ -1049,7 +1049,7 @@ nv98_chipset = { // .timer = nv04_timer_new, .fb = g84_fb_new, .imem = nv50_instmem_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, .bar = g84_bar_new, // .volt = nv40_volt_new, // .dma = nv50_dma_new, @@ -1078,7 +1078,7 @@ nva0_chipset = { .i2c = nv50_i2c_new, .imem = nv50_instmem_new, .mc = g98_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, // .timer = nv04_timer_new, @@ -1109,7 +1109,7 @@ nva3_chipset = { .i2c = g94_i2c_new, .imem = nv50_instmem_new, .mc = g98_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, // .therm = gt215_therm_new, @@ -1142,7 +1142,7 @@ nva5_chipset = { .i2c = g94_i2c_new, .imem = nv50_instmem_new, .mc = g98_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, // .therm = gt215_therm_new, @@ -1174,7 +1174,7 @@ nva8_chipset = { .i2c = g94_i2c_new, .imem = nv50_instmem_new, .mc = g98_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, // .therm = gt215_therm_new, @@ -1206,7 +1206,7 @@ nvaa_chipset = { .i2c = g94_i2c_new, .imem = nv50_instmem_new, .mc = g98_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, // .timer = nv04_timer_new, @@ -1237,7 +1237,7 @@ nvac_chipset = { .i2c = g94_i2c_new, .imem = nv50_instmem_new, .mc = g98_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, // .timer = nv04_timer_new, @@ -1268,7 +1268,7 @@ nvaf_chipset = { .i2c = g94_i2c_new, .imem = nv50_instmem_new, .mc = g98_mc_new, -// .mmu = nv50_mmu_new, + .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, // .therm = gt215_therm_new, @@ -1302,7 +1302,7 @@ nvc0_chipset = { .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf100_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, // .therm = gt215_therm_new, @@ -1337,7 +1337,7 @@ nvc1_chipset = { .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, // .therm = gt215_therm_new, @@ -1371,7 +1371,7 @@ nvc3_chipset = { .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, // .therm = gt215_therm_new, @@ -1405,7 +1405,7 @@ nvc4_chipset = { .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf100_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, // .therm = gt215_therm_new, @@ -1440,7 +1440,7 @@ nvc8_chipset = { .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf100_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, // .therm = gt215_therm_new, @@ -1475,7 +1475,7 @@ nvce_chipset = { .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf100_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, // .therm = gt215_therm_new, @@ -1510,7 +1510,7 @@ nvcf_chipset = { .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, // .therm = gt215_therm_new, @@ -1544,7 +1544,7 @@ nvd7_chipset = { .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, @@ -1576,7 +1576,7 @@ nvd9_chipset = { .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf110_pmu_new, // .therm = gf110_therm_new, @@ -1610,7 +1610,7 @@ nve4_chipset = { .imem = nv50_instmem_new, .ltc = gk104_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk104_pmu_new, // .therm = gf110_therm_new, @@ -1646,7 +1646,7 @@ nve6_chipset = { .imem = nv50_instmem_new, .ltc = gk104_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk104_pmu_new, // .therm = gf110_therm_new, @@ -1682,7 +1682,7 @@ nve7_chipset = { .imem = nv50_instmem_new, .ltc = gk104_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf110_pmu_new, // .therm = gf110_therm_new, @@ -1714,7 +1714,7 @@ nvea_chipset = { .imem = gk20a_instmem_new, .ltc = gk104_ltc_new, .mc = gk20a_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .pmu = gk20a_pmu_new, // .timer = gk20a_timer_new, // .volt = gk20a_volt_new, @@ -1742,7 +1742,7 @@ nvf0_chipset = { .imem = nv50_instmem_new, .ltc = gk104_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk110_pmu_new, // .therm = gf110_therm_new, @@ -1778,7 +1778,7 @@ nvf1_chipset = { .imem = nv50_instmem_new, .ltc = gk104_ltc_new, .mc = gf106_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk110_pmu_new, // .therm = gf110_therm_new, @@ -1814,7 +1814,7 @@ nv106_chipset = { .imem = nv50_instmem_new, .ltc = gk104_ltc_new, .mc = gk20a_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, // .therm = gf110_therm_new, @@ -1849,7 +1849,7 @@ nv108_chipset = { .imem = nv50_instmem_new, .ltc = gk104_ltc_new, .mc = gk20a_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, // .therm = gf110_therm_new, @@ -1884,7 +1884,7 @@ nv117_chipset = { .imem = nv50_instmem_new, .ltc = gm107_ltc_new, .mc = gk20a_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, // .therm = gm107_therm_new, @@ -1913,7 +1913,7 @@ nv124_chipset = { .imem = nv50_instmem_new, .ltc = gm107_ltc_new, .mc = gk20a_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, // .timer = gk20a_timer_new, @@ -1942,7 +1942,7 @@ nv126_chipset = { .imem = nv50_instmem_new, .ltc = gm107_ltc_new, .mc = gk20a_mc_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, // .timer = gk20a_timer_new, @@ -1967,8 +1967,8 @@ nv12b_chipset = { .imem = gk20a_instmem_new, .ltc = gm107_ltc_new, .mc = gk20a_mc_new, -// .mmu = gf100_mmu_new, -// .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, + .mmu = gf100_mmu_new, // .timer = gk20a_timer_new, // .ce[2] = gm204_ce2_new, // .dma = gf119_dma_new, diff --git a/drm/nouveau/nvkm/engine/device/gf100.c b/drm/nouveau/nvkm/engine/device/gf100.c index c9f8589c4..cf49c1d15 100644 --- a/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drm/nouveau/nvkm/engine/device/gf100.c @@ -31,7 +31,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; @@ -50,7 +49,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; @@ -69,7 +67,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; @@ -87,7 +84,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; @@ -106,7 +102,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; @@ -124,7 +119,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; @@ -142,7 +136,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; @@ -161,7 +154,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; @@ -179,7 +171,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/gk104.c b/drm/nouveau/nvkm/engine/device/gk104.c index 11a72fe23..df6aa5a98 100644 --- a/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drm/nouveau/nvkm/engine/device/gk104.c @@ -31,7 +31,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; @@ -51,7 +50,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; @@ -71,7 +69,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; @@ -89,7 +86,6 @@ gk104_identify(struct nvkm_device *device) break; case 0xea: device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; @@ -103,7 +99,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; @@ -123,7 +118,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; @@ -143,7 +137,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; @@ -162,7 +155,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; diff --git a/drm/nouveau/nvkm/engine/device/gm100.c b/drm/nouveau/nvkm/engine/device/gm100.c index cc1209bdd..3076601d4 100644 --- a/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drm/nouveau/nvkm/engine/device/gm100.c @@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 @@ -61,7 +60,6 @@ gm100_identify(struct nvkm_device *device) #endif device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -88,7 +86,6 @@ gm100_identify(struct nvkm_device *device) #endif device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -109,9 +106,7 @@ gm100_identify(struct nvkm_device *device) break; case 0x12b: - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv04.c b/drm/nouveau/nvkm/engine/device/nv04.c index 19a7a3be7..99e837f48 100644 --- a/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drm/nouveau/nvkm/engine/device/nv04.c @@ -29,7 +29,6 @@ nv04_identify(struct nvkm_device *device) switch (device->chipset) { case 0x04: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; @@ -38,7 +37,6 @@ nv04_identify(struct nvkm_device *device) break; case 0x05: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv10.c b/drm/nouveau/nvkm/engine/device/nv10.c index a5b222095..6f106f632 100644 --- a/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drm/nouveau/nvkm/engine/device/nv10.c @@ -29,14 +29,12 @@ nv10_identify(struct nvkm_device *device) switch (device->chipset) { case 0x10: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x15: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -45,7 +43,6 @@ nv10_identify(struct nvkm_device *device) break; case 0x16: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -54,7 +51,6 @@ nv10_identify(struct nvkm_device *device) break; case 0x1a: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -63,7 +59,6 @@ nv10_identify(struct nvkm_device *device) break; case 0x11: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -72,7 +67,6 @@ nv10_identify(struct nvkm_device *device) break; case 0x17: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -81,7 +75,6 @@ nv10_identify(struct nvkm_device *device) break; case 0x1f: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -90,7 +83,6 @@ nv10_identify(struct nvkm_device *device) break; case 0x18: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv20.c b/drm/nouveau/nvkm/engine/device/nv20.c index ad94aeb78..2a84c3ff8 100644 --- a/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drm/nouveau/nvkm/engine/device/nv20.c @@ -29,7 +29,6 @@ nv20_identify(struct nvkm_device *device) switch (device->chipset) { case 0x20: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -38,7 +37,6 @@ nv20_identify(struct nvkm_device *device) break; case 0x25: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -47,7 +45,6 @@ nv20_identify(struct nvkm_device *device) break; case 0x28: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -56,7 +53,6 @@ nv20_identify(struct nvkm_device *device) break; case 0x2a: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv30.c b/drm/nouveau/nvkm/engine/device/nv30.c index 61ca82736..b03249099 100644 --- a/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drm/nouveau/nvkm/engine/device/nv30.c @@ -29,7 +29,6 @@ nv30_identify(struct nvkm_device *device) switch (device->chipset) { case 0x30: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -38,7 +37,6 @@ nv30_identify(struct nvkm_device *device) break; case 0x35: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -47,7 +45,6 @@ nv30_identify(struct nvkm_device *device) break; case 0x31: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -57,7 +54,6 @@ nv30_identify(struct nvkm_device *device) break; case 0x36: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -67,7 +63,6 @@ nv30_identify(struct nvkm_device *device) break; case 0x34: device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv40.c b/drm/nouveau/nvkm/engine/device/nv40.c index 05a259cf3..9af8044c1 100644 --- a/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drm/nouveau/nvkm/engine/device/nv40.c @@ -30,7 +30,6 @@ nv40_identify(struct nvkm_device *device) case 0x40: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -43,7 +42,6 @@ nv40_identify(struct nvkm_device *device) case 0x41: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -56,7 +54,6 @@ nv40_identify(struct nvkm_device *device) case 0x42: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -69,7 +66,6 @@ nv40_identify(struct nvkm_device *device) case 0x43: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -82,7 +78,6 @@ nv40_identify(struct nvkm_device *device) case 0x45: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -95,7 +90,6 @@ nv40_identify(struct nvkm_device *device) case 0x47: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -108,7 +102,6 @@ nv40_identify(struct nvkm_device *device) case 0x49: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -121,7 +114,6 @@ nv40_identify(struct nvkm_device *device) case 0x4b: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -134,7 +126,6 @@ nv40_identify(struct nvkm_device *device) case 0x44: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -147,7 +138,6 @@ nv40_identify(struct nvkm_device *device) case 0x46: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -160,7 +150,6 @@ nv40_identify(struct nvkm_device *device) case 0x4a: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -173,7 +162,6 @@ nv40_identify(struct nvkm_device *device) case 0x4c: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -186,7 +174,6 @@ nv40_identify(struct nvkm_device *device) case 0x4e: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -199,7 +186,6 @@ nv40_identify(struct nvkm_device *device) case 0x63: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -212,7 +198,6 @@ nv40_identify(struct nvkm_device *device) case 0x67: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -225,7 +210,6 @@ nv40_identify(struct nvkm_device *device) case 0x68: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; diff --git a/drm/nouveau/nvkm/engine/device/nv50.c b/drm/nouveau/nvkm/engine/device/nv50.c index d72074f98..23cbb0f39 100644 --- a/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drm/nouveau/nvkm/engine/device/nv50.c @@ -31,7 +31,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; @@ -45,7 +44,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -62,7 +60,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -79,7 +76,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -96,7 +92,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -113,7 +108,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -130,7 +124,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -147,7 +140,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -164,7 +156,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -181,7 +172,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -198,7 +188,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -217,7 +206,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -235,7 +223,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -253,7 +240,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; diff --git a/drm/nouveau/nvkm/engine/dma/usernv04.c b/drm/nouveau/nvkm/engine/dma/usernv04.c index 2c2fb0988..c95942ef8 100644 --- a/drm/nouveau/nvkm/engine/dma/usernv04.c +++ b/drm/nouveau/nvkm/engine/dma/usernv04.c @@ -81,7 +81,7 @@ int nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_dmaobj **pdmaobj) { - struct nv04_mmu *mmu = nv04_mmu(dma); + struct nvkm_device *device = dma->engine.subdev.device; struct nv04_dmaobj *dmaobj; int ret; @@ -95,7 +95,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, return ret; if (dmaobj->base.target == NV_MEM_TARGET_VM) { - if (nv_object(mmu)->oclass == &nv04_mmu_oclass) + if (device->mmu->func == &nv04_mmu) dmaobj->clone = true; dmaobj->base.target = NV_MEM_TARGET_PCI; dmaobj->base.access = NV_MEM_ACCESS_RW; |