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* Experiments with large pagesbaserock/jetson/3.17-rc5Alexandre Courbot2014-08-274-9/+33
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* Revert "drm/nouveau/vm: fix mapping of SG pages list"Alexandre Courbot2014-08-271-7/+2
| | | | This reverts commit 8479bab3dabf349693e9c5716109a6d441b9d510.
* drm/nouveau: allocate GPFIFOs and fences coherentlyAlexandre Courbot2014-08-272-3/+3
| | | | | | | | Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to allow them to be safely accessed by the kernel without being synced on non-coherent architectures. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm/nouveau: synchronize BOs when requiredAlexandre Courbot2014-08-273-0/+56
| | | | | | | | | | | | | | On architectures for which access to GPU memory is non-coherent, caches need to be flushed and invalidated explicitly when BO control changes between CPU and GPU. This patch adds buffer synchronization functions which invokes the correct API (PCI or DMA) to ensure synchronization is effective. Based on the TTM DMA cache helper patches by Lucas Stach. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm/nouveau: implement explicitly coherent BOsAlexandre Courbot2014-08-272-8/+73
| | | | | | | | | | | | | | Allow nouveau_bo_new() to recognize the TTM_PL_FLAG_UNCACHED flag, which means that we want the allocated BO to be perfectly coherent between the CPU and GPU. This is useful on non-coherent architectures for which we do not want to manually sync some rarely-accessed buffers: typically, fences and pushbuffers. A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent architecture will be populated using the DMA API, and accesses to it performed using the coherent mapping performed by dma_alloc_coherent(). Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm/nouveau: introduce nv_device_is_cpu_coherent()Alexandre Courbot2014-08-272-0/+8
| | | | | | | | | | | Add a function allowing us to know whether a device is CPU-coherent, i.e. accesses performed by the CPU on GPU-mapped buffers will be immediately visible on the GPU side and vice-versa. For now, a device is considered to be coherent if it uses the PCI bus on a non-ARM architecture. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* drm/nouveau/vm: fix mapping of SG pages listAlexandre Courbot2014-08-271-2/+7
| | | | | | | | | | | | | | SG pages lists (not to be confused with scatterlists) are a list of 4KB memory pages used to define a nouveau_mem. Mapping them to a VM that does not use 4KB apertures resulted in each subsequent 4KB physical page being mapped into a larger VM aperture, thus creating an incorrect, overlapping mapping. This patch fixes this issue by detecting when such mappings occur and by skipping the required number of pages in the list to ensure a correct linear mapping. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* [HACK] add gk20a instmemAlexandre Courbot2014-08-278-9/+192
| | | | | This is a gazillion times faster, but requires to invalidate the GPU L2 (probably at a better place than this!)
* HACK: drm/nouveau: prime: Pin buffer objects to VRAMThierry Reding2014-08-271-2/+31
| | | | | | | | | This is currently required to work around the lack of proper SMMU support on Tegra. Ideally buffer objects could always be pinned to GART and the SMMU will take care of mapping them to a linear I/O virtual address range for importers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* therm/nv84+: do not expose non-calibrated internal temp sensorMartin Peres2014-08-281-1/+6
| | | | | Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* therm: make sure the temperature settings are sane on nv84+Martin Peres2014-08-284-1/+35
| | | | | | | | | | | | One of my nv92 has a calibrated internal sensor but it displays 0°C as the default values use sw calibration values to force the temperature to 0. Since we cannot read the temperature from the adt7473 present on this board, let's re-enable the internal reading! Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* subdev: add a pfuse subdev v2Martin Peres2014-08-2821-1/+380
| | | | | | | | | | | | We will use this subdev to disable temperature reading on cards that did not get a sensor calibration in the factory. v2: - rename "nouveau_fuse_rd32" to "gxXXX_fuse_rd32" as adviced by Christian Costa - fold the code a little as adviced by Emil Velikov Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/nva3: Set intermediate core clock on reclockingRoy Spliet2014-08-283-14/+51
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/nva3: For PLL clocks always make sure the PLL is not in useRoy Spliet2014-08-281-0/+9
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/nva3: Abort when PLL doesn't lockRoy Spliet2014-08-281-1/+5
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/nva3: HOST clockRoy Spliet2014-08-282-8/+78
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/nva3: Set PLL refclkRoy Spliet2014-08-283-29/+48
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/nva3: Parse clock control registers more accuratelyRoy Spliet2014-08-281-4/+28
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: Fix duplicate definition of NV04_PFB_BOOT_0_*Pierre Moreau2014-08-254-32/+25
| | | | | Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: Display Nouveau boot options at launchPierre Moreau2014-08-259-6/+37
| | | | | | | | | It can help to remove any ambiguity about which options were passed to Nouveau, especially in case the user had some options set in /etc/modprobe.d/*.conf that he forgot about, as they won't appear in a dmesg. Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr: wait for scrubbers to finish before uploading new ucodeBen Skeggs2014-08-251-3/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr/fuc: make $r1-$r10 registers callee-saved in kernel.fucMartin Peres2014-08-255-736/+749
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr/fuc: add ld/st macrosMartin Peres2014-08-251-0/+10
| | | | | Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr: add helpers for delay-to-ticks and ticks-to-delayMartin Peres2014-08-259-2284/+2446
| | | | | Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr: add some arith functions (mul32_32_64, subu64 and addu64)Martin Peres2014-08-2512-1736/+1922
| | | | | Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr: fix the timers implementation with concurent processesMartin Peres2014-08-255-990/+1133
| | | | | | | | | | | | | | | | | | The problem with the current implementation is that adding a timer improperly checked which process would time up first by not taking into account how much time elapsed since their timer got scheduled. Rework the re-scheduling decision t fix this. The catch with this fix is that we are limited to scheduling timers of up to 2^31 ticks to avoid any potential overflow. Since we are unlikely to need to wait for more than a second, this won't be a problem :) Another possible fix would be to decrement the timeouts of all processes but it would duplicate a lot of code and dealing with edge cases wasn't pretty last time I checked. Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ppwr: enable ppwr on gm107Martin Peres2014-08-252-1/+5
| | | | | | | | For some reason, it is now required to wait a 20 µs after the 0x200 reset of the engine. Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gm107/therm: add PWM fan support v2Martin Peres2014-08-259-7/+109
| | | | | | | | v2: change the copyright ownership from "Nouveau Community" to myself, as per Illia's recommendation. Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* therm/fan: do not use the pwm mode when the vbios tells us to use toggleMartin Peres2014-08-251-1/+7
| | | | | Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios/fan: add support for maxwell's fan management table v2Martin Peres2014-08-257-2/+115
| | | | | | | | | | | | Re-use the therm-exported fan structure with only two minor modifications: - pwm_freq: u16 -> u32; - add fan_type (toggle or PWM) v2: - Do not memset the table to 0 as it erases the pre-set default values Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ltc: allocate tagram from memory that spans all partitionsBen Skeggs2014-08-251-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* core/mm: allow allocation to be confined to a specific slice of heapBen Skeggs2014-08-2516-26/+38
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* core/mm: fill in holes with "allocated" nodesBen Skeggs2014-08-252-6/+21
| | | | | | | | | | | The allocation algorithm doesn't expect there to be holes in the mm, which causes its alignment/cutoff calculations to choke (and go negative) when encountering the last chunk of a block before a hole. The least expensive solution is to simply fill in any holes with nodes that are pre-marked as being allocated. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* core/mm: dump mm when trying to tear one down that still has allocationsBen Skeggs2014-08-251-9/+32
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* core/mm: modify test for if building a mm with holes in itBen Skeggs2014-08-252-2/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* core/mm: make it clearer what (type == 0) meansBen Skeggs2014-08-252-9/+10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ltc/gf100: translate interrupt status into more meaningful namesBen Skeggs2014-08-252-5/+29
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ltc: drop workaround for an interrupt storm that no longer happensBen Skeggs2014-08-252-10/+0
| | | | | | | | | This is really the wrong thing to do, but at the time it was our only option to prevent worse issues. We no longer cause quite so much anger from LTC, so it's not needed. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* kms/nv50-: wait for completion interrupts instead of pollingBen Skeggs2014-08-251-19/+42
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp/nv50-: add support for completion eventsBen Skeggs2014-08-2511-11/+173
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* core: pass related object into notify constructorBen Skeggs2014-08-2518-28/+42
| | | | | | The event source types/index might need to be derived from it. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bar: ioremap only the areas that we're actually usingBen Skeggs2014-08-252-20/+19
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* nvif: distinguish nvif_unpack/unvers as being macrosBen Skeggs2014-08-1534-76/+76
| | | | | Reported-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* platform: fix compilation errorAlexandre Courbot2014-08-151-1/+2
| | | | | | | | nouveau_platform.c was still using the old nouveau_dev() macro, triggering a compilation error. Fix this. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gk20a: add LTC deviceAlexandre Courbot2014-08-151-0/+1
| | | | | | | LTC device is now required for PGRAPH to work, add it. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: warn if we fail to re-pin fb on resumeBen Skeggs2014-08-151-1/+3
| | | | | | Spotted by Coverity. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* nvif: fix dac load detect method definitionBen Skeggs2014-08-151-2/+2
| | | | | | | | A thinko made me turn this into a u16 when cleaning up. Spotted by coverity. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gr/gf100-: fix -ENOSPC detection when allocating zbc table entriesBen Skeggs2014-08-151-0/+6
| | | | | | Spotted by Coverity. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* nvif: return null pointers on failure, in addition to ret != 0Ben Skeggs2014-08-152-2/+6
| | | | | | | | Reported by Coverity. The intention is that the return value is checked, but let's be more paranoid and make it extremely obvious if something forgets to. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ltc: fix tag base address getting truncated if above 4GiBBen Skeggs2014-08-151-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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