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*---. Merge branches 'staging/fixes', 'staging/gm20b_clk', 'staging/ioctls' and ↵baserock/tegra/4.3Alexandre Courbot2015-12-1838-227/+4119
|\ \ \ | | | | | | | | | | | | 'staging/secure_boot' into staging/work
| | | * sb: move to subdevAlexandre Courbot2015-12-1812-150/+225
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| | | * sb: use acr_ucode_load name for loading-only HS FWAlexandre Courbot2015-12-181-1/+1
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| | | * Revert "sb: bunch of printks"Alexandre Courbot2015-12-111-161/+4
| | | | | | | | | | | | | | | | This reverts commit efeb5c37b95cb90507de2bcbe72f7c999dcad8d2.
| | | * sb: bunch of printksAlexandre Courbot2015-12-111-4/+161
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| | | * gm206: enable secure bootAlexandre Courbot2015-12-111-0/+4
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| | | * gm204: enable secure bootAlexandre Courbot2015-12-112-7/+5
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| | | * gr/gf100: force FB domain if using FECS bootloaderAlexandre Courbot2015-12-111-0/+4
| | | | | | | | | | | | | | | | Unneeded? Seems to work fine without this...
| | | * gr/gm20b: warn if secure boot cannot be performedAlexandre Courbot2015-12-111-1/+6
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| | | * sb: force size and align of LS blob for dGPUAlexandre Courbot2015-12-111-1/+1
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| | | * sb: complete HS falcon desc structureAlexandre Courbot2015-12-111-1/+7
| | | | | | | | | | | | | | | | There are unused for now, but for the sake of completeness...
| | | * sb: handle WPR properly for dGPUAlexandre Courbot2015-12-111-15/+42
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| | | * sb: use new BL descriptor formatAlexandre Courbot2015-12-111-13/+22
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| | | * sb: align resident code and data sizeAlexandre Courbot2015-12-111-2/+2
| | | | | | | | | | | | | | | | | | | | Otherwise ACR will complain when copying. Shouldn't that be fixed in ACR?
| | | * sb: make ACR use PRI to load GPCCS FWAlexandre Courbot2015-12-111-0/+4
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| | | * sb: set instance block location properly for dGPU as wellAlexandre Courbot2015-12-111-1/+7
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| | | * sb: add FWs at tail of listAlexandre Courbot2015-12-111-1/+1
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| | | * sb: fix indentationAlexandre Courbot2015-12-111-1/+1
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| | | * sb: add some docAlexandre Courbot2015-12-111-1/+6
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| | | * sb: move struct aroundAlexandre Courbot2015-12-111-28/+28
| | | | | | | | | | | | | | | | Makes code easier to read
| | | * secure_boot: add GPCCS FW handlingAlexandre Courbot2015-12-111-13/+35
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| | | * secureboot: move to device init so VRAM is availableAlexandre Courbot2015-12-111-5/+5
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| | | * gm20b: secure-boot FECS falconAlexandre Courbot2015-12-112-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | Enable secure boot of FECS for GM20B. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| | | * gr: support for securely-booted FECS firmwareAlexandre Courbot2015-12-111-10/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trigger the loading of FECS/GPCCS using secure boot if required, and start managed falcons using the CPUCTL_ALIAS register since CPUCTL is protected in that case. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| | | * core: add support for secure bootAlexandre Courbot2015-12-115-0/+1809
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On GM20x and later GPUs, firmware for some essential falcons (notably FECS) must be authenticated by a NVIDIA-produced signature and loaded by a high-secure falcon in order to access certain registers, in a process known as Secure Boot. Secure Boot requires the building of a binary blob containing the firmwares and signatures of the falcons to be loaded. This blob is then given to a high-secure falcon running a signed loader firmware that copies the blob into a write-protected region, checks that the signatures are valid, and finally loads the verified firmware into the managed falcons and switches them to a priviledged mode. This patch adds code that performs this process using PMU as the high-secure falcon, and wires it into the device core. Currently, only the secure loading of the FECS firmware is handled, but support for other falcons (notably GPCCS and PMU) is upcoming. The reason for limiting to FECS is that GR must initiate the loading of FECS at init time, which, being managed by secure boot, will trigger the loading of all other managed firmwares. A solution to this needs to be discussed. This code is tested on Tegra/GM20B and some minor work is required for dGPU support, but the fundations are here for general support of Secure Boot. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| | * | merge tiling, rename infoAlexandre Courbot2015-12-114-65/+57
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| | * | drm/nouveau: Support fence fd's at kickoffLauri Peltonen2015-12-114-1/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new NOUVEAU_GEM_PUSHBUF_2 ioctl that accepts and emits a sync fence fd from/to user space if the user space requests it by passing corresponding flags. The new ioctl is only supported on relatively new chips, and it does not support relocations or suffix0/suffix1. Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> [acourbot@nvidia.com: carry upstream, fix style] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| | * | gem: Split nv50_dma_pushLauri Peltonen2015-12-113-12/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split this function to provide a version allowing to directly specify a PB entry in its hardware format. Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> [acourbot@nvidia.com: split from longer patch] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| | * | drm/nouveau: Add fence fd helpersLauri Peltonen2015-12-112-1/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nouveau_fence_install, which installs a drm fence as a file descriptor that can be returned to user space. Add nouveau_fence_sync_fd, which pushes semaphore wait commands for each Nouveau fence contained within the sync fd. If the sync fd contains non-Nouveau fences, those are waited on the CPU. Add missing fence_value_str and timeline_value_str callbacks to nouveau fence_ops. Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> [acourbot@nvidia.com: carry patch upstream] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| | * | drm/nouveau: Split nouveau_fence_syncLauri Peltonen2015-12-116-59/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split nouveau_fence_sync to two functions: * nouveau_fence_sync, which only adds a fence wait to the channel command stream, and * nouveau_bo_sync, which gets the fences from the reservation object and passes them to nouveau_fence_sync. This factorizes the code in the new nouveau_fence_sync() which was present twice otherwise. Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> [acourbot@nvidia.com: factorize code some more, fix style] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| | * | drm/nouveau: add GEM_SET_TILING staging ioctlAri Hirvonen2015-12-117-21/+95
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new NOUVEAU_GEM_SET_TILING ioctl to set correct tiling mode for imported dma-bufs. This ioctl is staging for now and enabled with the "staging_tiling" module option. Signed-off-by: Ari Hirvonen <ahirvonen@nvidia.com> [acourbot@nvidia.com: carry upstream, many fixes] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| * | clk/gm20b: #ifdef Tegra-specific codeAlexandre Courbot2015-12-181-1/+3
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| * | clk/gk20a: introduce mnp structAlexandre Courbot2015-12-111-20/+26
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| * | optimize gm20bAlexandre Courbot2015-12-111-3/+2
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| * | move stuff around...Alexandre Courbot2015-12-113-138/+111
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| * | clk/gk20a: convert parameters to khz for more precisionAlexandre Courbot2015-12-111-13/+14
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| * | gm20b: quick insertion of clock driverAlexandre Courbot2015-12-114-0/+1426
| | | | | | | | | | | | Need to factorize all the code in common with GK20A
| * | volt: add GM20B driverAlexandre Courbot2015-12-114-0/+119
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| * | drm/nouveau/volt: gk20a: make some reusable functions non-staticVince Hsu2015-12-112-18/+51
| | | | | | | | | | | | | | | | | | | | | The CVB calculation and voltage setting functions can be reused for the future chips. So move the declaration to gk20a.h. Signed-off-by: Vince Hsu <vinceh@nvidia.com>
| * | drm/nouveau/volt: add function get_voltage_by_id()Vince Hsu2015-12-113-0/+11
| | | | | | | | | | | | | | | | | | | | | We need the exact voltage value to calculate the PLL coefficients for GM20B. Signed-off-by: Vince Hsu <vinceh@nvidia.com>
| * | add speedo GPU ID informationAlexandre Courbot2015-12-113-3/+5
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| * | add pll_g reference clockAlexandre Courbot2015-12-112-0/+17
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* | gr: rename gf100_gr_wait_idle for gk104_*Xia Yang2015-12-186-45/+46
| | | | | | | | | | | | | | | | | | The status bit used in gf100_gr_wait_idle only exists starting gk104. As the function is currently used in gk20a and later, rename the function to use gk104 prefix to reflex correct supported chip version. Signed-off-by: Xia Yang <xiay@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
* | fifo/gk104: fix chid bit maskXia Yang2015-12-181-2/+2
| | | | | | | | | | | | | | | | | | | | Fix the channel id bit mask in FIFO schedule timeout error handling. FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000. FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff. Signed-off-by: Xia Yang <xiay@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
* | WIP flush mmu when needed (?)Alexandre Courbot2015-12-181-0/+4
| | | | | | | | See https://chromium-review.googlesource.com/#/c/305610/3
* | gm20b: gr: flush LTC (from Chrome)Alexandre Courbot2015-12-181-0/+4
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* | instmem/gk20a: add write barrier when releasing DMA objectAlexandre Courbot2015-12-181-0/+2
| | | | | | | | | | | | | | | | | | When using the DMA-API for instmem, we may obtain a write-combined mapping. For such cases, add a write barrier in gk20a_instobj_release_dma() to make sure that all writes have reached memory at this time. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* | fifo/gm20b: kick channel during cleanupAlexandre Courbot2015-12-185-24/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GM20B requires a channel kick to be performed during gpfifo cleanup, or the FIFO will attempt to fetch memory from the previous context as a channel is recycled. A previous commit attempted to do this for all Kepler GPUs, but due to bug reports that pinned it down it has been reverted. The present commit limits its scope to GM20B only. The only effective change of this patch is to add a call to gk104_fifo_gpfifo_kick() in gpfifo_fini for GM20B, but doing so requires to export quite a few extra functions, hence its non-trivial length. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* | allow compilation against 3.18Alexandre Courbot2015-12-185-0/+42
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* | tegra: compile fixesAlexandre Courbot2015-12-112-0/+4
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