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* Comments and testsdrfAlexandre Courbot2015-11-101-16/+35
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* hwref: usage macros and docsKen Adams2015-11-102-0/+211
| | | | | | | Included is a scheme to reference the hwref definitions which NVIDA uses internally called the "drf def" system. Signed-off-by: Ken Adams <kadams@nvidia.com>
* hwref: hardware reference headersKen Adams2015-11-10598-0/+59004
| | | | | | | | These headers are generated from NVIDIA-internal hardware manuals. For this check-in all chips Nouveau supports >= nv50/g80 are included. Signed-off-by: Ken Adams <kadams@nvidia.com>
* instmem/gk20a: do not use non-portable dma_to_phys()Alexandre Courbot2015-11-101-3/+7
| | | | | | | | | dma_to_phys() is not guaranteed to be available on all platforms and should not be used outside of arch/. Replace it with what it is expected to do in our case: simply cast the DMA handle to a physical address. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* fifo/gm20b: kick channel during cleanupAlexandre Courbot2015-11-095-24/+121
| | | | | | | | | | | | | | GM20B requires a channel kick to be performed during gpfifo cleanup, or the FIFO will attempt to fetch memory from the previous context as a channel is recycled. A previous commit attempted to do this for all Kepler GPUs, but due to bug reports that pinned it down it has been reverted. The present commit limits its scope to GM20B only. The only effective change of this patch is to add a call to gk104_fifo_gpfifo_kick() in gpfifo_fini for GM20B, but doing so requires to export quite a few extra functions, hence its non-trivial length. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* instmem/gk20a: fix race conditionsAlexandre Courbot2015-11-091-29/+37
| | | | | | | | | | | | | | | The LRU list used for recycling CPU mappings was handling concurrency very poorly. For instance, if an instobj was acquired twice before being released once, it would end up into the LRU list even though there is still a client accessing it. This patch fixes this by properly counting how many clients are currently using a given instobj. While at it, we also raise errors when inconsistencies are detected, and factorize some code. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* tegra: compile fixesAlexandre Courbot2015-11-093-6/+11
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* nvkm: add/remove 0's to make 7 (or 9)-nibble constants use 8 nibblesIlia Mirkin2015-11-053-6/+6
| | | | | Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* volt/pwm/gk104: fix an off-by-one resulting in the voltage not being setMartin Peres2015-11-051-1/+1
| | | | | Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Martin Peres <martin.peres@free.fr>
* pci: enable c800 magic for some unknown Samsung laptopBen Skeggs2015-11-051-1/+7
| | | | | | fdo#70354 - comment #88. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* kms: no need to check for empty edid before drm_detect_hdmi_monitorIlia Mirkin2015-11-051-1/+0
| | | | | Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci: enable c800 magic for Clevo P157SMKarol Herbst2015-11-051-1/+7
| | | | | | this is needed for my gpu Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* core: fix return in error path of device probeAlexandre Courbot2015-11-051-1/+2
| | | | | | | We want to unlock nv_devices_mutex in this error path as well. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* kms: allow 225/297MHz pixel clocks for HDMI on Fermi/KeplerIlia Mirkin2015-11-041-3/+21
| | | | | | | | | Some Fermi's apparently alow allow 297MHz clocks, so create a parameter which allows end-users to set it themselves until we have a reliable way to determine the board's maximum pixel clocks. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp: activate dual link TMDS links only when possibleHauke Mehrtens2015-11-043-6/+13
| | | | | | | | | | | | | Without this patch a pixel clock rate above 165 MHz on a TMDS link is assumed to be dual link. This is true for DVI, but not for HDMI. HDMI supports no dual link, but it supports pixel clock rates above 165 MHz. Only activate Dual Link mode when it is actually possible and requested. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> [imirkin: check for hdmi monitor for computing proto, use sor ctrl to enable extra config bit] Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: bump patchlevel to indicate availability of abi16/nvif interopBen Skeggs2015-11-031-1/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* abi16: implement limited interoperability with usif/nvifBen Skeggs2015-11-033-2/+53
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* abi16: introduce locked variant of nouveau_abi16_get()Ben Skeggs2015-11-031-5/+13
| | | | | | | USIF already takes the client mutex, but will need access to ABI16 data in order to provide some limited interoperability. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* abi16: remove unused argument from nouveau_abi16_get()Ben Skeggs2015-11-033-9/+8
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci: enable c800 magic for Medion Erazer X7827Ilia Mirkin2015-11-031-0/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91557 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci: enable c800 magic for Lenovo Y510PIlia Mirkin2015-11-031-1/+7
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70354#c75 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pll/gk104: fix PLL instability due to bad configuration with gddr5Karol Herbst2015-11-031-23/+77
| | | | | | | | | | | | | | | | | | | | | | | | | This patch uses an approach closer to the nvidia driver to configure both PLLs for high gddr5 memory clocks (usually above 2400MHz) Previously nouveau used the one PLL as it was used for the lower clocks and just adjusted the second PLL to get as close as possible to the requested clock. This means for my card, that I got a 4050 MHz clock although 4008 MHz was requested. Now the driver iterates over a list of PLL configuration also used by the nvidia driver and then adjust the second PLL to get near the requested clock. Also it hold to some restriction I found while analyzing the PLL configurations This won't fix all gddr5 high clock issues itself, but it should be fine on hybrid gpu systems as found on many laptops these days. Also switching while normal desktop usage should be a lot more stable than before. v2: move the pll code into ramgk104 Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/g84: Enable reclocking for GDDR3 G94-G200Roy Spliet2015-11-031-1/+1
| | | | | | | | Your milage may vary, as it's only been tested on a single G94 and one G96. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bus/hwsq: Implement VBLANK waiting heuristicRoy Spliet2015-11-035-2/+41
| | | | | | | | | Avoids waiting for VBLANKS that never arrive on headless or otherwise unconventional set-ups. Strategy taken from MEMX. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnv50: Script changes for G94 and upRoy Spliet2015-11-031-6/+30
| | | | | | | | | | | 10053c is not even read on some cards, and I have no idea exactly what the criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables all features that are never used. The practical effect should be the same as this implementation though. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnv50: Deal with cards without timing entriesRoy Spliet2015-11-033-7/+50
| | | | | | | | Like Pierre's G94. We might want to structure Kepler similarly in a follow-up. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnv50: Voltage GPIOsRoy Spliet2015-11-032-0/+42
| | | | | | | | Does not seem to be necessary for NVA0, hence untested by me. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramgt215: Restructure r111100 calculation for DDR2Roy Spliet2015-11-031-30/+34
| | | | | | | | Seems to be mostly equal to DDR3 on < GT218, should improve stability for DDR2 reclocks. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramgt215: Change FBVDD/Q when BIOS asks for itRoy Spliet2015-11-033-0/+20
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific to genericRoy Spliet2015-11-032-24/+19
| | | | | | | | In preparation of changing FBVDDQ, as observed on at least one GDDR3 card. While at it, adhere to func.log[1] properly for consistency. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios/rammap: Identify DLLoff for >= GF100Roy Spliet2015-11-035-12/+39
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci: Handle 5-bit and 8-bit tag fieldPierre Moreau2015-11-036-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the hardware supports extended tag field (8-bit ones), then enable it. This is usually done by the VBIOS, but not on some MBPs (see fdo#86537). In case extended tag field is not supported, 5-bit tag field is used which limits the possible number of requests to 32. Apparently bits 7:0 of 0x08841c stores some number of outstanding requests, so cap it to 32 if extended tag is unsupported. Fixes: fdo#86537 v2: Restrict changes to chipsets >= 0x84 v3: * Add nvkm_pci_mask to pci.h * Mask bit 8 before setting it v4: * Rename `add` argument of nvkm_pci_mask to `value` * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset checks v5: * Rebase code on latest PCI structure * Restore PCIe check * Fix namings in nvkm_pci_mask * Rephrase part of the commit message Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp,pm: constify nvkm_object_func structuresJulia Lawall2015-11-032-2/+2
| | | | | | | | | | These nvkm_object_func structures are never modified. All other nvkm_object_func structures are declared as const. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gr: add FERMI_COMPUTE_B class to GF110+Ilia Mirkin2015-11-033-0/+3
| | | | | | | | GF110+ supports both the A and B compute classes, make sure to accept both. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gr: document mp error 0x10Ilia Mirkin2015-11-031-0/+1
| | | | | | | | | NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE, which apparently happens when trying to use an atomic operation on local or shared memory (instead of global memory). Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: fix memory leakSudip Mukherjee2015-11-031-1/+3
| | | | | | | | If pm_runtime_get_sync() we were going to "out" but we missed freeing vma. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: remove unused functionSudip Mukherjee2015-11-032-15/+0
| | | | | | | | | | coverity.com reported that memset was using a buffer of size 0, on checking the code it turned out that the function was not being used. So remove it. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pmu/gk107: enable PGOB codepathsBen Skeggs2015-11-031-1/+1
| | | | | | Reported to be needed as per fdo#70354 comment #61. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pmu/gk104: check fuse to determine presence of PGOBBen Skeggs2015-11-031-0/+4
| | | | | | | Not 100% confirmed, but seems to match from the few boards I've looked at so far. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci: prepare for chipset-specific initialisation tasksBen Skeggs2015-11-032-0/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci/nv46: attempt to fix msi, and re-enable by defaultBen Skeggs2015-11-036-12/+12
| | | | | | | | Was not able to obtain a trace of NVRM due to kernel version annoyances, however, experimentally confirmed that the WAR we use on NV50/G8x boards works here too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci/g94: split implementation from nv40Ben Skeggs2015-11-036-26/+67
| | | | | | | An upcoming patch will implement functionality that we don't use on any NV40 chipset. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci/g84: split implementation from nv50Ben Skeggs2015-11-036-5/+49
| | | | | | | An upcoming patch will implement functionality that we don't use on the original NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ibus/gf100: increase wait timeout to avoid read faultsSamuel Pitoiset2015-11-036-4/+77
| | | | | | | | | | | | Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gm204/6: add voltage control using the new gk104 volt classMartin Peres2015-11-031-0/+2
| | | | | | | | | | I got confirmation that we can read and change the voltage with the same code. The divider is also computed correctly on the gm204 we got our hands on. Thanks to Yoshimo on IRC for executing the tests on his gm204! Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gm107: add voltage control using the new gk104 volt classMartin Peres2015-11-031-0/+1
| | | | | | | Let's ignore the other desktop Maxwells until I get my hands on one and confirm that we still can change the voltage. Signed-off-by: Martin Peres <martin.peres@free.fr>
* volt/gk104: add support for pwm and gpio modesMartin Peres2015-11-036-7/+133
| | | | | | | | | | | | | Most Keplers actually use the GPIO-based voltage management instead of the new PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles the case where no GPIOs exist. All the Maxwells seem to use the PWM method though. v2: - Do not forget to commit the PWM configuration change! Signed-off-by: Martin Peres <martin.peres@free.fr>
* volt: add support for non-vid-based voltage controllersMartin Peres2015-11-032-1/+12
| | | | | | | | This patch is not ideal but it definitely beats a rewrite of the current interface and is very self-contained. Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios/volt: add support for pwm-based volt managementMartin Peres2015-11-032-3/+29
| | | | | Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ttm: set the DMA mask for platform devicesAlexandre Courbot2015-11-031-6/+19
| | | | | | | | | | So far the DMA mask was not set for platform devices, which limited them to a 32-bit physical space. Allow dma_set_mask() to be called for non-PCI devices, and also take the IOMMU bit into account since it could restrict the physically addressable space. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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