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* [HACK] fix video memory mappingsgk20a_vramAlexandre Courbot2014-11-121-1/+3
| | | | | | | | On GK20A video memory is actually system memory. Make sure it is mapped without compressed storage types, and with the L2 cache disabled. This is all the more reason for RAM-less devices to report 0 VRAM and have user-space allocate all their objects in system memory.
* HACK: drm/nouveau: prime: Pin buffer objects to VRAMThierry Reding2014-11-121-2/+31
| | | | | | | | | This is currently required to work around the lack of proper SMMU support on Tegra. Ideally buffer objects could always be pinned to GART and the SMMU will take care of mapping them to a linear I/O virtual address range for importers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* fb/ramgk20a: use mm_nodesAlexandre Courbot2014-11-121-11/+13
| | | | | | | This is how VRAM objects are defined on other GPUs, and this saves us from caveats when mapping large pages. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* Revert "[HACK] add gk20a instmem"Alexandre Courbot2014-11-128-192/+9
| | | | This reverts commit c9eeb89a4daf95f34b70d659f0eb467c5c606e2b.
* [HACK] add gk20a instmemAlexandre Courbot2014-11-128-9/+192
| | | | | This is a gazillion times faster, but requires to invalidate the GPU L2 (probably at a better place than this!)
* platform: support for netlist firmwaresAlexandre Courbot2014-11-123-5/+74
| | | | | | | | | | | | Netlists released by NVIDIA are made of a single file containing firmwares that can potentially be used across different engines. It therefore makes most sense to load a netlist once before engines are probed and have them duplicate their firmwares so the netlist can be freed at the end of probe. This patch implements this mechanism and adds the lookup data for GK20A. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* graph/nvc0: add support for netlist firmwaresAlexandre Courbot2014-11-123-0/+173
| | | | | | | | | | | NVIDIA is releasing some GPU firmwares for the Tegra SoCs under linux-firmware. The release format is a single file (called a netlist) containing all the firmwares relevant to a GPU, which must thus be extracted. This patch adds support for parsing the netlist and loading the firmwares for the NVC0 family of GPUs, falling back to the previous firmware lookup method is no netlist was already loaded. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* docAlexandre Courbot2014-11-123-0/+56
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* [DEBUG] Add channel dumping functions for NVEAAlexandre Courbot2014-11-123-0/+226
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* fb/gk20a: fix setting of large page size bitAlexandre Courbot2014-11-121-1/+15
| | | | | | | | Commit "ltc/gf100-: fix cbc issues on certain boards" moved the setting of the large page size bit from bar/nvc0 to fb/nvc0. GK20A uses its own FB device and the change was thus not applied to it - fix this. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* nv50/disp: Fix modeset on G94Roy Spliet2014-11-111-2/+23
| | | | | | | | | | | | | | | | | Commit 1dce6264045cd23e9c07574ed0bb31c7dce9354f introduced a regression spotted on several G94 (FDObz #85160). This device seems to expect the vblank period to be set after setting scale instead of before. V2: shove this in a separate function This is a candidate bug-fix for 3.18 Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Zlatko Calusic <zcalusic@bitsync.net> Tested-by: Michael Riesch <michael@riesch.at> Tested-by: "poma" <pomidorabelisima@gmail.com> Tested-by: Adam Williamson <adamw@happyassassin.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: we need pin_refcnt for nouveau_bo_placement_set()Ben Skeggs2014-11-101-5/+9
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* kms/nv50-: add some evo tracing ability for debuggingBen Skeggs2014-11-101-0/+13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* kms/nv50: use sclass() instead of trial-and-errorBen Skeggs2014-11-101-6/+20
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* kms/nv50: remove a couple of cursor-related stub functionsBen Skeggs2014-11-102-12/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: fix pin refcnt leak in failure pathBen Skeggs2014-11-101-12/+12
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: synchronize BOs when requiredAlexandre Courbot2014-11-103-0/+56
| | | | | | | | | | | | | | | On architectures for which access to GPU memory is non-coherent, caches need to be flushed and invalidated explicitly when BO control changes between CPU and GPU. This patch adds buffer synchronization functions which invokes the correct API (PCI or DMA) to ensure synchronization is effective. Based on the TTM DMA cache helper patches by Lucas Stach. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: allocate GPFIFOs and fences coherentlyAlexandre Courbot2014-11-102-3/+3
| | | | | | | | | Specify TTM_PL_FLAG_UNCACHED when allocating GPFIFOs and fences to allow them to be safely accessed by the kernel without being synced on non-coherent architectures. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: implement explicitly coherent BOsAlexandre Courbot2014-11-102-8/+73
| | | | | | | | | | | | | | | Allow nouveau_bo_new() to recognize the TTM_PL_FLAG_UNCACHED flag, which means that we want the allocated BO to be perfectly coherent between the CPU and GPU. This is useful on non-coherent architectures for which we do not want to manually sync some rarely-accessed buffers: typically, fences and pushbuffers. A TTM BO allocated with the TTM_PL_FLAG_UNCACHED on a non-coherent architecture will be populated using the DMA API, and accesses to it performed using the coherent mapping performed by dma_alloc_coherent(). Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: introduce nv_device_is_cpu_coherent()Alexandre Courbot2014-11-102-0/+8
| | | | | | | | | | | | Add a function allowing us to know whether a device is CPU-coherent, i.e. accesses performed by the CPU on GPU-mapped buffers will be immediately visible on the GPU side and vice-versa. For now, a device is considered to be coherent if it uses the PCI bus on a non-ARM architecture. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: warn when moving a pinned objectAlexandre Courbot2014-11-101-2/+9
| | | | | | | | | Pinned BOs are supposed to remain in their current location until unpinned. Display a warning for the supposedly-erroneous case where we are trying to move such objects. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp: clear notify intr status when enabling, to prevent racesBen Skeggs2014-11-062-0/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp/nv50-: rename class members to match nvidia channel namesBen Skeggs2014-11-0611-206/+206
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* core: remove some dead code that got forgottenBen Skeggs2014-11-063-135/+0
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bin: default to libnvkm driver for tools that touch registersBen Skeggs2014-11-065-5/+5
| | | | | | | | The DRM won't allow device registers to be touched by userspace, so it's pointless to even try that backend, and it's annoying to have to pass "-b lib" to everything if the DRM is loaded. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pwr/fuc: Fix thinko in nouveau_memx_wait()Roy Spliet2014-11-061-1/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clock/nva3: Allow user reclockingRoy Spliet2014-11-061-1/+1
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnva3: Reclocking script for GDDR3Roy Spliet2014-11-062-10/+92
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnva3: Reclocking script for DDR2Roy Spliet2014-11-061-15/+42
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnva3: Reclocking script for DDR3Roy Spliet2014-11-063-75/+219
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnva3: Ressurect timing calculation codeRoy Spliet2014-11-063-14/+132
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnva3: Link training for DDR3Roy Spliet2014-11-0610-1415/+2259
| | | | | | | V2: fix whitespace errors in memx.fuc Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/gddr3: Generate MR valuesRoy Spliet2014-11-065-0/+121
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios/ramcfg: 10_02_40 -> DLLoffRoy Spliet2014-11-064-4/+4
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: move the (far too many...) different s/r paths to the same placeBen Skeggs2014-11-062-138/+144
| | | | | | No code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fifo/gk104-: handle copy engine class errorsBen Skeggs2014-11-061-6/+42
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: stop after NV+NPDS+ISBN imageBen Skeggs2014-11-061-4/+9
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: add some more signatures as seen on my gtx660Ben Skeggs2014-11-062-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: add support for gm204Ben Skeggs2014-11-063-11/+16
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* device: recognise GM204Ben Skeggs2014-11-062-1/+45
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp/gm204: some magic that fixes bringup of uninitialised outputsBen Skeggs2014-11-065-3/+24
| | | | | | | | | | | Probably missing something here, doesn't make a lot of sense to write or+link data into a register whose offset is calculated by the same or+link info.. This is the all I've witnessed the binary driver and vbios doing so far, so it'll do. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp/gm204: initial supportBen Skeggs2014-11-0611-1/+259
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp/gf110-: magic that might help some tmds issuesBen Skeggs2014-11-061-2/+10
| | | | | | | | The binary driver has been doing this since GF119, and we've somehow gotten away with it. But, TMDS that hasn't been initialised already by the x86 vbios code is distorted without it on GM204. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: support for opcodes 0x47/0x48Ben Skeggs2014-11-061-0/+36
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: add support for udisp 2.2Ben Skeggs2014-11-061-0/+1
| | | | | | Not entirely sure why this got bumped at all yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: add support for dp 4.1Ben Skeggs2014-11-061-1/+9
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* i2c: add support for DCB_I2C_PMGR port typeBen Skeggs2014-11-061-0/+12
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: add support for ccb 4.1Ben Skeggs2014-11-062-7/+25
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: add support for dcb 4.1Ben Skeggs2014-11-061-12/+15
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* i2c/gm204: add aux channel driverBen Skeggs2014-11-069-4/+236
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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