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* PMU wipgm20bAlexandre Courbot2015-10-2210-11/+2022
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* fifo/gm20b: kick channel during cleanupAlexandre Courbot2015-10-225-24/+121
| | | | | | | | | | | | | | GM20B requires a channel kick to be performed during gpfifo cleanup, or the FIFO will attempt to fetch memory from the previous context as a channel is recycled. A previous commit attempted to do this for all Kepler GPUs, but due to bug reports that pinned it down it has been reverted. The present commit limits its scope to GM20B only. The only effective change of this patch is to add a call to gk104_fifo_gpfifo_kick() in gpfifo_fini for GM20B, but doing so requires to export quite a few extra functions, hence its non-trivial length. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* instmem/gk20a: exclusively acquire instobjsAlexandre Courbot2015-10-221-9/+6
| | | | Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* Compile fixes for GM20BAlexandre Courbot2015-10-222-1/+2
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* Compile fixesAlexandre Courbot2015-10-133-5/+7
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* clk/g84: Enable reclocking for GDDR3 G94-G200Roy Spliet2015-10-121-1/+1
| | | | | | | | Your milage may vary, as it's only been tested on a single G94 and one G96. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bus/hwsq: Implement VBLANK waiting heuristicRoy Spliet2015-10-125-2/+41
| | | | | | | | | Avoids waiting for VBLANKS that never arrive on headless or otherwise unconventional set-ups. Strategy taken from MEMX. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnv50: Script changes for G94 and upRoy Spliet2015-10-121-6/+30
| | | | | | | | | | | 10053c is not even read on some cards, and I have no idea exactly what the criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables all features that are never used. The practical effect should be the same as this implementation though. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnv50: Deal with cards without timing entriesRoy Spliet2015-10-123-7/+50
| | | | | | | | Like Pierre's G94. We might want to structure Kepler similarly in a follow-up. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnv50: Voltage GPIOsRoy Spliet2015-10-122-0/+42
| | | | | | | | Does not seem to be necessary for NVA0, hence untested by me. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramgt215: Restructure r111100 calculation for DDR2Roy Spliet2015-10-121-30/+34
| | | | | | | | Seems to be mostly equal to DDR3 on < GT218, should improve stability for DDR2 reclocks. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramgt215: Change FBVDD/Q when BIOS asks for itRoy Spliet2015-10-123-0/+20
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramgt215: Transform GPIO ramfuc method from FBVREF-specific to genericRoy Spliet2015-10-122-24/+19
| | | | | | | | In preparation of changing FBVDDQ, as observed on at least one GDDR3 card. While at it, adhere to func.log[1] properly for consistency. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios/rammap: Identify DLLoff for >= GF100Roy Spliet2015-10-125-12/+39
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci: Handle 5-bit and 8-bit tag fieldPierre Moreau2015-10-126-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the hardware supports extended tag field (8-bit ones), then enable it. This is usually done by the VBIOS, but not on some MBPs (see fdo#86537). In case extended tag field is not supported, 5-bit tag field is used which limits the possible number of requests to 32. Apparently bits 7:0 of 0x08841c stores some number of outstanding requests, so cap it to 32 if extended tag is unsupported. Fixes: fdo#86537 v2: Restrict changes to chipsets >= 0x84 v3: * Add nvkm_pci_mask to pci.h * Mask bit 8 before setting it v4: * Rename `add` argument of nvkm_pci_mask to `value` * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset checks v5: * Rebase code on latest PCI structure * Restore PCIe check * Fix namings in nvkm_pci_mask * Rephrase part of the commit message Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* disp,pm: constify nvkm_object_func structuresJulia Lawall2015-10-122-2/+2
| | | | | | | | | | These nvkm_object_func structures are never modified. All other nvkm_object_func structures are declared as const. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gr: add FERMI_COMPUTE_B class to GF110+Ilia Mirkin2015-10-123-0/+3
| | | | | | | | GF110+ supports both the A and B compute classes, make sure to accept both. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gr: document mp error 0x10Ilia Mirkin2015-10-121-0/+1
| | | | | | | | | NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE, which apparently happens when trying to use an atomic operation on local or shared memory (instead of global memory). Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: fix memory leakSudip Mukherjee2015-10-121-1/+3
| | | | | | | | If pm_runtime_get_sync() we were going to "out" but we missed freeing vma. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: remove unused functionSudip Mukherjee2015-10-122-15/+0
| | | | | | | | | | coverity.com reported that memset was using a buffer of size 0, on checking the code it turned out that the function was not being used. So remove it. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* WIPpmu/gk107: enable PGOB codepathsBen Skeggs2015-10-121-1/+1
| | | | | | Reported to be needed as per fdo#70354 comment #61. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* WIPpmu/gk104: check fuse to determine presence of PGOBBen Skeggs2015-10-121-0/+4
| | | | | | | Not 100% confirmed, but seems to match from the few boards I've looked at so far. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci: prepare for chipset-specific initialisation tasksBen Skeggs2015-10-122-0/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci/nv46: attempt to fix msi, and re-enable by defaultBen Skeggs2015-10-126-12/+12
| | | | | | | | Was not able to obtain a trace of NVRM due to kernel version annoyances, however, experimentally confirmed that the WAR we use on NV50/G8x boards works here too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci/g94: split implementation from nv40Ben Skeggs2015-10-126-26/+67
| | | | | | | An upcoming patch will implement functionality that we don't use on any NV40 chipset. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pci/g84: split implementation from nv50Ben Skeggs2015-10-126-5/+49
| | | | | | | An upcoming patch will implement functionality that we don't use on the original NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ibus/gf100: increase wait timeout to avoid read faultsSamuel Pitoiset2015-10-126-4/+77
| | | | | | | | | | | | Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gm204/6: add voltage control using the new gk104 volt classMartin Peres2015-10-121-0/+2
| | | | | | | | | | I got confirmation that we can read and change the voltage with the same code. The divider is also computed correctly on the gm204 we got our hands on. Thanks to Yoshimo on IRC for executing the tests on his gm204! Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gm107: add voltage control using the new gk104 volt classMartin Peres2015-10-121-0/+1
| | | | | | | Let's ignore the other desktop Maxwells until I get my hands on one and confirm that we still can change the voltage. Signed-off-by: Martin Peres <martin.peres@free.fr>
* volt/gk104: add support for pwm and gpio modesMartin Peres2015-10-126-7/+133
| | | | | | | | | | | | | Most Keplers actually use the GPIO-based voltage management instead of the new PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles the case where no GPIOs exist. All the Maxwells seem to use the PWM method though. v2: - Do not forget to commit the PWM configuration change! Signed-off-by: Martin Peres <martin.peres@free.fr>
* volt: add support for non-vid-based voltage controllersMartin Peres2015-10-122-1/+12
| | | | | | | | This patch is not ideal but it definitely beats a rewrite of the current interface and is very self-contained. Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios/volt: add support for pwm-based volt managementMartin Peres2015-10-122-3/+29
| | | | | Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ttm: set the DMA mask for platform devicesAlexandre Courbot2015-10-121-6/+19
| | | | | | | | | | So far the DMA mask was not set for platform devices, which limited them to a 32-bit physical space. Allow dma_set_mask() to be called for non-PCI devices, and also take the IOMMU bit into account since it could restrict the physically addressable space. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ttm: convert to DMA APIAlexandre Courbot2015-10-121-7/+5
| | | | | | | | The pci_dma_* functions are now superseeded in the kernel by the DMA API. Make the conversion to this more generic API. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* instmem/gk20a: make use of the IOMMU bitAlexandre Courbot2015-10-121-4/+6
| | | | | | | | Use the IOMMU bit specified in platform data instead of hardcoding it to the bit used by current Tegra GPUs. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* platform: allow to specify the IOMMU bitAlexandre Courbot2015-10-126-10/+46
| | | | | | | | | | | Current Tegra code taking advantage of the IOMMU assumes a hardcoded value for the IOMMU bit. Make it a platform property instead for flexibility. v2 (Ben Skeggs): remove nvkm dependence on drm structures Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* instmem/gk20a: use direct CPU accessAlexandre Courbot2015-10-122-116/+317
| | | | | | | | | | | | | | | | | | | | | | | | | | The Great Nouveau Refactoring Take II brought us a lot of goodness, including acquire/release methods that are called before and after an instobj is modified. These functions can be used as synchronization points to manage CPU/GPU coherency if we modify an instobj using the CPU. This patch replaces the legacy and slow PRAMIN access for gk20a instmem with CPU mappings and writes. A LRU list is used to unmap unused mappings after a certain threshold (currently 1MB) of mapped instobjs is reached. This allows mappings to be reused most of the time. Accessing instobjs using the CPU requires to maintain the GPU L2 cache, which we do in the acquire/release functions. This triggers a lot of L2 flushes/invalidates, but most of them are performed on an empty cache (and thus return immediately), and overall context setup performance greatly benefits from this (from 250ms to 160ms on Jetson TK1 for a simple libdrm program). Making L2 management more explicit should allow us to grab some more performance in the future. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm: remove unnecessary usage of object handlesBen Skeggs2015-10-1210-61/+31
| | | | | | | No longer required in a lot of cases, as objects are identified over NVIF via an alternate mechanism since the rework. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ltc/gf100: add flush/invalidate functionsAlexandre Courbot2015-10-125-0/+39
| | | | | | | | Allow clients to manually flush and invalidate L2. This will be useful for Tegra systems for which we want to write instmem using the CPU. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* ltc: add hooks for invalidate and flushAlexandre Courbot2015-10-123-0/+20
| | | | | | | | These are useful for systems without a coherent CPU/GPU bus. For such systems we may need to maintain the L2 ourselves. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* timer: re-introduce nvkm_wait_xsec macrosAlexandre Courbot2015-10-121-0/+10
| | | | | | | | | Reintroduce macros allowing us to test a register against a certain mask, since this is the most common usage pattern for the more generic nvkm_xsec macros and makes the code more concise and readable. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pmu: do not assume a PMU is presentAlexandre Courbot2015-10-121-1/+1
| | | | | | | | | Some devices may not have a PMU. Avoid a NULL pointer dereference in such cases by checking whether the pointer given to nvkm_pmu_pgob() is valid. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: fix OF loadingIlia Mirkin2015-10-123-11/+36
| | | | | | | | | | | | | | | Currently OF bios load fails for a few reasons: - checksum failure - bios size too small - no PCIR header - bios length not a multiple of 4 In this change, we resolve all of the above by ignoring any checksum failures (since OF VBIOS tends not to have a checksum), and faking the PCIR data when loading from OF. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fbcon: take runpm reference when userspace has an open fdBen Skeggs2015-10-121-0/+24
| | | | | | | | | | | We need to do this in order to prevent accesses to the device while it's powered down. Userspace may have an mmap of the fb, and there's no good way (that I know of) to prevent it from touching the device otherwise. This fixes some nasty races between runpm and plymouth on some systems, which result in the GPU getting very upset and hanging the boot. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* nouveau: Disable AGP for SiS 761Ondrej Zary2015-10-122-2/+9
| | | | | | | | | | | | | SiS 761 chipset does not support AGP cards but has AGP capability (for the onboard video). At least PC Chips A31G board using this chipset has an AGP-like AGPro slot that's wired to the PCI bus. Enabling AGP will fail (GPU lockup and software fbcon, X11 hangs). Add support for matching just the host bridge in nvkm_device_agp_quirks and add entry for SiS 761 with mode 0 (AGP disabled). Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* display: allow up to 16k width/height for fermi+Ilia Mirkin2015-10-121-1/+5
| | | | | Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios: translate devinit pri/sec i2c bus to internal identifiersBen Skeggs2015-10-121-0/+6
| | | | | | | | fdo#92013. Regression from "i2c: transition pad/ports away from being based on nvkm_object" Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* v4.3-rc5Ben Skeggs2015-10-123-5/+5
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* device: enable c800 quirk for tecra w50Ben Skeggs2015-09-111-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/gt215: Unbreak engine pausing for GT21x/MCP7xRoy Spliet2015-09-111-1/+1
| | | | | | | | Typo that snuck in with commit 6979c6303a4abf263753cd9d577d79f05c6e8c47 Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Reported-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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