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* gr/gm20b: don't bypass MMU security checkoldstagingbaserock/gk20aVince Hsu2015-08-061-5/+0
| | | | | | | | The MMU security check was bypassed for non-secure boot earlier. We have to enable it as we have secure boot supported now. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* gr/gm20b: add MaxwellDmaCopyA classMark Zhang2015-08-061-0/+1
| | | | | | | | | | | This patch adds class MaxwellDmaCopyA which makes GR init gets called during nouveau probing which makes secure boot works. [alex] Looks like a hack rather than an actual fix. Secure boot should just work. Signed-off-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* mmu: fix sgt mappings that span multiple pde'sLauri Peltonen2015-08-061-0/+2
| | | | | Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
* HACK fix gk20aAlexandre Courbot2015-08-061-1/+1
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* drm/nouveau/clk: add clocking driver for GM20BVince Hsu2015-08-063-0/+1396
| | | | | | | | | | | | | | | | | | This patch adds GPCPLL support for GM20B. The GPCPLL inside GM20B has improvements compared with GK20A - Glitchless post divider - Noise Aware PLL (NA-PLL) - Glitchless Sync Mux The glitchless pdiv is enabled by default. The NA-PLL is only supported on the parts that have GPU speedo ID larger than one and enabled if available. All the the clock programming sequences are from the work and effort by: Alex Frid <afrid@nvidia.com> Signed-off-by: Vince Hsu <vinceh@nvidia.com>
* drm/nouveau/volt: add volt support for GM20BVince Hsu2015-08-063-0/+134
| | | | | | | The CVB calculation equation is the same as GK20A. Only the CVB constants are newly added. Signed-off-by: Vince Hsu <vinceh@nvidia.com>
* drm/nouveau/volt: gk20a: make some reusable functions non-staticVince Hsu2015-08-062-18/+51
| | | | | | | The CVB calculation and voltage setting functions can be reused for the future chips. So move the declaration to gk20a.h. Signed-off-by: Vince Hsu <vinceh@nvidia.com>
* drm/nouveau/volt: add function get_voltage_by_id()Vince Hsu2015-08-061-0/+10
| | | | | | | We need the exact voltage value to calculate the PLL coefficients for GM20B. Signed-off-by: Vince Hsu <vinceh@nvidia.com>
* drm/nouveau/platform: add gpu_speedo_id informationVince Hsu2015-08-061-1/+1
| | | | | | Get GPU speedo ID from fuse to setup clock programming later. Signed-off-by: Vince Hsu <vinceh@nvidia.com>
* Some comments for GK20AAlexandre Courbot2015-08-063-0/+25
| | | | This reverts commit 9495a0bcfb62849a1f9a7647c8dd1b9e0dd52a04.
* bios: add opcodes 0x73 and 0x77Ilia Mirkin2015-07-281-0/+37
| | | | | | | | No known VBIOSes use these, but they are present in the actual VBIOS table parsing logic. No harm in adding these too. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* device: recognize GM20BAlexandre Courbot2015-07-281-0/+20
| | | | | | | Recognize GM20B and assign the right engines and subdevs. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gr: add GM20B supportAlexandre Courbot2015-07-289-6/+216
| | | | | | | | | Add support for GM20B's graphics engine, based on GK20A. Note that this code alone will not allow the engine to initialize on released devices which require PMU-assisted secure boot. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fifo: add GM20B fifoAlexandre Courbot2015-07-284-1/+40
| | | | | | | GM20B has a 512-channels FIFO similar to GK104. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gr/gk20a: use same initialization sequence as nvgpuAlexandre Courbot2015-07-285-30/+421
| | | | | | | | | | | | | GK20A's initialization was based on GK104, but differences exist in the way the initial context is built and the initialization process itself. This patch follows the same initialization sequence as nvgpu performs to avoid bad surprises. Since the register bundles initialization also differ considerably from GK104, the register packs are now loaded from firmware files, again similarly to what is done with nvgpu. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* gr: use NVIDIA-provided external firmwaresAlexandre Courbot2015-07-281-12/+19
| | | | | | | | | NVIDIA will officially start providing GR firmwares through linux-firmware for GPUs that require it. Change the GR firmware lookup function to use these files. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm/gk104: add compute signals/sourcesSamuel Pitoiset2015-07-283-1/+93
| | | | | | | | | These signals and sources have been reverse engineered from CUPTI (Linux). Graphics signals exposed by PerfKit (Windows only) will be added later. I need to reverse engineer them and it's a bit painful. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm/gk104: re-use gf100_pm_ctor()Samuel Pitoiset2015-07-282-55/+13
| | | | | | | gk104_pm_ctor() is equal to gf100_pm_ctor(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm/nv40: rename pcounter domains to 'pc' instead of 'pm'Samuel Pitoiset2015-07-281-1/+1
| | | | | | | | This trivial patch makes thing more consistent since hardware signals names are prefixed by 'pcXX'. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: expose name of domainsSamuel Pitoiset2015-07-281-0/+1
| | | | | | | | This is going to be very useful for GF100+ because each GPC can have its own domain of counters. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/clk: fix tstate to pstate calculationWei Ni2015-07-281-1/+1
| | | | | | | | | | | | | According to the tstate calculation in nvkm_clk_tstate(), the range of tstate is from -(clk->state_nr - 1) to 0, it mean the tstate is negative value. But in nvkm_pstate_work(), it use (clk->state_nr - 1 - clk->tstate) to limit pstate, it's not correct. This patch fix it to use (clk->state_nr - 1 + clk->tstate) to limit pstate. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: some fixes related to sourcesSamuel Pitoiset2015-07-281-5/+16
| | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: fix signals/sources for GT200+Samuel Pitoiset2015-07-282-6/+5
| | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm/gf100: add compute signals/sourcesSamuel Pitoiset2015-07-286-5/+280
| | | | | | | | | | | These signals and sources have been reverse engineered from CUPTI (Linux). Graphics signals exposed by PerfKit (Windows only) will be added later. I need to reverse engineer them and it's a bit painful. This commit also adds a new class for GF108 and GF117. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm/gf100: allow to share GPC, HUB and PART domainsSamuel Pitoiset2015-07-283-18/+33
| | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: stack perfdom class under perfmonBen Skeggs2015-07-281-7/+31
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: swap perfmon/perfdom code to avoid forward decl in next commitBen Skeggs2015-07-281-175/+175
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm/nv50: add compute and graphics signals/sourcesSamuel Pitoiset2015-07-287-11/+484
| | | | | | | | | | | These signals and sources have been reverse engineered from NVIDIA PerfKit (Windows) and CUPTI (Linux), they will be used to build complex hardware events from the userspace. This commit also adds a new class for GT200. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: allow the userspace to configure sourcesSamuel Pitoiset2015-07-282-10/+94
| | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: allow to configure domains instead of simple countersSamuel Pitoiset2015-07-284-109/+129
| | | | | | | | | | | | | | | | | | | Configuring counters from the userspace require the kernel to handle some logic related to performance counters. Basically, it has to find a free slot to assign a counter, to handle extra counting modes like B4/B6 and it must return and error when it can't configure a counter. In my opinion, the kernel should not handle all of that logic but it should only write the configuration sent by the userspace without checking anything. In other words, it should overwrite the configuration even if it's already counting and do not return any errors. This patch allows the userspace to configure a domain instead of separate counters. This has the advantage to move all of the logic to the userspace. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: allow the userspace to schedule hardware countersSamuel Pitoiset2015-07-282-23/+42
| | | | | | | | | | | | | This adds a new method NVIF_PERFCTR_V0_INIT which starts a batch of hardware counters for sampling. This will allow the userspace to start a monitoring session using the INIT method and to stop it with SAMPLE, for example before and after a frame is rendered. This commit temporarily breaks nv_perfmon but this is going to be fixed with the upcoming patch. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: implement NVIF_PERFMON_V0_QUERY_SOURCE methodSamuel Pitoiset2015-07-281-0/+77
| | | | | | | | This allows to query the ID, the mask and the user-readable name of sources for each signal. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: allow to query the number of sources for a signalSamuel Pitoiset2015-07-281-3/+19
| | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: add concept of sourcesSamuel Pitoiset2015-07-282-4/+102
| | | | | | | | | | | | | A source (or multiplexer) is a tuple addr+mask+shift which allows to control a block of signals. The maximum number of sources that a signal can define is arbitrary limited to 8 and this should be large enough. This patch allows to define multi-level of sources for a signal. Each different sources are stored to a global list and will be exposed to the userspace through the nvif interface in order to avoid conflicts. Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: allow to monitor hardware signal index 0x00Samuel Pitoiset2015-07-283-6/+10
| | | | | | | | | This signal index must be always allowed even if it's not clearly defined in a domain in order to monitor a counter like 0x03020100 because it's the default value of signals. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: use hardware signals indexes instead of user-readable namesSamuel Pitoiset2015-07-281-40/+12
| | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: change signal iter to u16Samuel Pitoiset2015-07-282-6/+6
| | | | | | | | 16 bits is large enough to store the maximum number of signals available for one domain (i.e. 256). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: allow to query signals by domainSamuel Pitoiset2015-07-281-24/+12
| | | | | | | | This will allow to configure performance counters with hardware signal indexes instead of user-readable names in an upcoming patch. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: implement NVIF_PERFMON_V0_QUERY_DOMAIN methodSamuel Pitoiset2015-07-281-0/+86
| | | | | | | | This allows to query the number of available domains, including the number of hardware counter and the number of signals per domain. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: prevent creating a perfctr object when signals are not foundSamuel Pitoiset2015-07-281-2/+4
| | | | | | | | Since a new class has been introduced to query signals, we can now return an error when the userspace wants to monitor unknown signals. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: reorganize the nvif interfaceSamuel Pitoiset2015-07-281-6/+32
| | | | | | | | | This commit introduces the NVIF_IOCTL_NEW_V0_PERFMON class which will be used in order to query domains, signals and sources. This separates the querying and the counting interface. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: remove unused nvkm_perfsig_wrap() functionSamuel Pitoiset2015-07-282-24/+0
| | | | | | Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* pm: remove pmu signalsSamuel Pitoiset2015-07-287-147/+1
| | | | | | | | PDAEMON signals don't have to be exposed by the perfmon engine. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* clk/nv50: Enable user reclocking for NVA0Roy Spliet2015-07-281-1/+2
| | | | | | | | Tested on a few cards. Probably works quite well for most, given they should all be GDDR3. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/gddr3: Add a few CL and WR entries observed on GTX260Roy Spliet2015-07-281-4/+4
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnv50: GDDR3 script for NVA0Roy Spliet2015-07-281-25/+104
| | | | | | | | | This looks surprisingly similar to scripts on earlier cards as well but they don't seem to work just yet. That... and I don't have any, which makes it a tough job to reverse engineer. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios/ramcfg: Separate out RON pull valueRoy Spliet2015-07-283-3/+8
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* bios/rammap: Parse perf mode as if it's a rammap entryRoy Spliet2015-07-282-0/+17
| | | | | | | Some of the bits in there are similar to the bits in the gt215 rammap. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramnv50: Ressurect timing code, use proper timing/rammap handlersRoy Spliet2015-07-282-33/+164
| | | | | | | Might need some generalisation to < GT200. For those: use at your own risk! Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* fb/ramgt215: No need to cuss like thatRoy Spliet2015-07-281-1/+1
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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