path: root/drm/nouveau/include/nvkm/hwref/gf108/nv_graphics_nobundle_hwref.h

/*
 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */
#ifndef __nv_gf108_graphics_nobundle_hwref_h__
#define __nv_gf108_graphics_nobundle_hwref_h__

#define NV_PGRAPH_INTR                                    0x400100
#define NV_PGRAPH_INTR_NOTIFY                                  0:0
#define NV_PGRAPH_INTR_NOTIFY_RESET                              1
#define NV_PGRAPH_INTR_SEMAPHORE                               1:1
#define NV_PGRAPH_INTR_SEMAPHORE_RESET                           1
#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT                       2:2
#define NV_PGRAPH_INTR_SEMAPHORE_TIMEOUT_RESET                   1
#define NV_PGRAPH_INTR_ILLEGAL_METHOD                          4:4
#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET                      1
#define NV_PGRAPH_INTR_ILLEGAL_CLASS                           5:5
#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET                       1
#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY                          6:6
#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET                      1
#define NV_PGRAPH_INTR_FIRMWARE_METHOD                         8:8
#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET                     1
#define NV_PGRAPH_INTR_FECS_ERROR                            19:19
#define NV_PGRAPH_INTR_FECS_ERROR_RESET                          1
#define NV_PGRAPH_INTR_CLASS_ERROR                           20:20
#define NV_PGRAPH_INTR_CLASS_ERROR_RESET                         1
#define NV_PGRAPH_INTR_EXCEPTION                             21:21
#define NV_PGRAPH_INTR_EXCEPTION_RESET                           1
#define NV_PGRAPH_INTR_EN                                 0x40013c
#define NV_PGRAPH_FECS_INTR                               0x400144
#define NV_PGRAPH_EXCEPTION                               0x400108
#define NV_PGRAPH_EXCEPTION_FE                                 0:0
#define NV_PGRAPH_EXCEPTION_MEMFMT                             1:1
#define NV_PGRAPH_EXCEPTION_DS                                 4:4
#define NV_PGRAPH_EXCEPTION_GPC                              24:24
#define NV_PGRAPH_EXCEPTION1                              0x400118
#define NV_PGRAPH_EXCEPTION1_GPC                              31:0
#define NV_PGRAPH_EXCEPTION2                              0x40011c
#define NV_PGRAPH_EXCEPTION_EN                            0x400138
#define NV_PGRAPH_EXCEPTION_EN_FE                              0:0
#define NV_PGRAPH_EXCEPTION1_EN                           0x400130
#define NV_PGRAPH_EXCEPTION2_EN                           0x400134
#define NV_PGRAPH_CLASS_ERROR                             0x400110
#define NV_PGRAPH_CLASS_ERROR_CODE                            15:0
#define NV_PGRAPH_NONSTALL_INTR                           0x400120
#define NV_PGRAPH_NONSTALL_INTR_TRAP                           1:1
#define NV_PGRAPH_GRFIFO_CONTROL                          0x400500
#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS                        0:0
#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS            16:16
#define NV_PGRAPH_GRFIFO_STATUS                           0x400504
#define NV_PGRAPH_TRAPPED_ADDR                            0x400704
#define NV_PGRAPH_TRAPPED_ADDR_MTHD                           13:2
#define NV_PGRAPH_TRAPPED_ADDR_SUBCH                         18:16
#define NV_PGRAPH_TRAPPED_DATA_LOW                        0x400708
#define NV_PGRAPH_TRAPPED_DATA_HIGH                       0x40070c
#define NV_PGRAPH_STATUS                                  0x400700
#define NV_PGRAPH_STATUS_FE_METHOD_UPPER                       1:1
#define NV_PGRAPH_STATUS_FE_METHOD_LOWER                       2:2
#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE                    0
#define NV_PGRAPH_STATUS_MASK                             0x400610
#define NV_PGRAPH_STATUS1                                 0x400604
#define NV_PGRAPH_STATUS2                                 0x400608
#define NV_PGRAPH_ENGINE_STATUS                           0x40060c
#define NV_PGRAPH_ENGINE_STATUS_VALUE                          0:0
#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY                       1
#define NV_PGRAPH_ACTIVITY0                               0x400380
#define NV_PGRAPH_ACTIVITY1                               0x400384
#define NV_PGRAPH_ACTIVITY2                               0x400388
#define NV_PGRAPH_ACTIVITY4                               0x400390
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS                     0x400200
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE                   15:0
#define NV_PGRAPH_PIPE_BUNDLE_DATA                        0x400204
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG                      0x400208
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE      31:31
#define NV_PGRAPH_PRI_FE_HWW_ESR                          0x404000
#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET                       30:30
#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE                    1
#define NV_PGRAPH_PRI_FE_HWW_ESR_EN                          31:31
#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE                       1
#define NV_PGRAPH_PRI_FE_GO_IDLE_ON_STATUS                0x404150
#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT                  0x404154
#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT                31:0
#define NV_PGRAPH_PRI_FE_GO_IDLE_CHECK                    0x404158
#define NV_PGRAPH_PRI_FE_PWR_MODE                         0x404170
#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE                         1:0
#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO                      0
#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON                  2
#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ                          4:4
#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE                       0
#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND                       1
#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i)        (0x404200+((i)*4))
#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS                 15:0
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX                0x404488
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE             31:31
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER         1
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA                 0x40448c
#define NV_PGRAPH_PRI_MME_HWW_ESR                         0x404490
#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET                      30:30
#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE                   1
#define NV_PGRAPH_PRI_MME_HWW_ESR_EN                         31:31
#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE                      1
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR                      0x404600
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET                   30:30
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE                1
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN                      31:31
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE                   1
#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX0                0x409040
#define NV_PGRAPH_PRI_FECS_FALCON_MAILBOX1                0x409044
#define NV_PGRAPH_PRI_FECS_FALCON_IDLESTATE               0x40904c
#define NV_PGRAPH_PRI_FECS_FALCON_OS                      0x409080
#define NV_PGRAPH_PRI_FECS_FALCON_RM                      0x409084
#define NV_PGRAPH_PRI_FECS_FALCON_DEBUGINFO               0x409094
#define NV_PGRAPH_PRI_FECS_FALCON_ENGCTL                  0x4090a4
#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL                  0x409100
#define NV_PGRAPH_PRI_FECS_FALCON_CPUCTL_STARTCPU              1:1
#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC                 0x409104
#define NV_PGRAPH_PRI_FECS_FALCON_BOOTVEC_VEC                 15:0
#define NV_PGRAPH_PRI_FECS_FALCON_HWCFG                   0x409108
#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL                  0x40910c
#define NV_PGRAPH_PRI_FECS_FALCON_DMACTL_REQUIRE_CTX           0:0
#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFBASE              0x409110
#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFMOFFS             0x409114
#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD               0x409118
#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_IMEM               4:4
#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_WRITE              5:5
#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_SIZE              10:8
#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFCMD_CTXDMA           14:12
#define NV_PGRAPH_PRI_FECS_FALCON_DMATRFFBOFFS            0x40911c
#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC(i)     (0x409180+((i)*16))
#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_OFFS                   7:2
#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_BLK                   15:8
#define NV_PGRAPH_PRI_FECS_FALCON_IMEMC_AINCW                24:24
#define NV_PGRAPH_PRI_FECS_FALCON_IMEMD(i)     (0x409184+((i)*16))
#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT(i)     (0x409188+((i)*16))
#define NV_PGRAPH_PRI_FECS_FALCON_IMEMT_TAG                   15:0
#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC(i)      (0x4091c0+((i)*8))
#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_OFFS                   7:2
#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_BLK                   15:8
#define NV_PGRAPH_PRI_FECS_FALCON_DMEMC_AINCW                24:24
#define NV_PGRAPH_PRI_FECS_FALCON_DMEMD(i)      (0x4091c4+((i)*8))
#define NV_PGRAPH_PRI_FECS_CURRENT_CTX                    0x409b00
#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_PTR                    27:0
#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET                29:28
#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_TARGET_VID_MEM            0
#define NV_PGRAPH_PRI_FECS_CURRENT_CTX_VALID                 31:31
#define NV_PGRAPH_PRI_FECS_NEW_CTX                        0x409b04
#define NV_PGRAPH_PRI_FECS_NEW_CTX_PTR                        27:0
#define NV_PGRAPH_PRI_FECS_NEW_CTX_TARGET                    29:28
#define NV_PGRAPH_PRI_FECS_NEW_CTX_VALID                     31:31
#define NV_PGRAPH_PRI_FECS_METHOD_DATA                    0x409500
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH                    0x409504
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR                    11:0
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_BIND_POINTER          3
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_HALT_PIPELINE         4
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE  16
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE       9
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN       21
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE        22
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE         0x25
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE    0x30
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE      0x31
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS    0x32
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_STOP_CTXSW         0x38
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_START_CTXSW        0x39
#define NV_PGRAPH_PRI_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT           0x21
#define NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE                0x409420
#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0              0x409c00
#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1                 0x409400
#define NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1_ARB_BUSY           12:12
#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS                0x409c18
#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD         17:17
#define NV_PGRAPH_PRI_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD          18:18
#define NV_PGRAPH_PRI_FECS_HOST_INT_CLEAR                 0x409c20
#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE                0x409c24
#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW            16:16
#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE         1
#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD         17:17
#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE      1
#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD          18:18
#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE       1
#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG          19:19
#define NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE       1
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL                0x409614
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_HALT            0:0
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_HALT            1:1
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_HALT             2:2
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET    4:4
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED         1
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET    5:5
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED         1
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET     6:6
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED          1
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET   8:8
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED         0
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED        1
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET   9:9
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED         0
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED        1
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET  10:10
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED          0
#define NV_PGRAPH_PRI_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED         1
#define NV_PGRAPH_PRI_FECS_CTX_STATE_STORE_MAJOR_REV_ID   0x40960c
#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX(i)     (0x409800+((i)*4))
#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX__SIZE_1                 8
#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE                31:0
#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_PASS              1
#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_VALUE_FAIL              2
#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET(i) (0x409820+((i)*4))
#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_SET_VALUE            31:0
#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR(i)           (0x409840+((i)*4))
#define NV_PGRAPH_PRI_FECS_CTXSW_MAILBOX_CLEAR_VALUE          31:0
#define NV_PGRAPH_PRI_FECS_FS                             0x409604
#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_GPCS               4:0
#define NV_PGRAPH_PRI_FECS_FS_NUM_AVAILABLE_FBPS             20:16
#define NV_PGRAPH_PRI_FECS_CFG_FALCON                     0x409620
#define NV_PGRAPH_PRI_FECS_CFG_FALCON_IMEM_SZ                  7:0
#define NV_PGRAPH_PRI_FECS_RC_LANES                       0x409880
#define NV_PGRAPH_PRI_FECS_RC_LANES_NUM_CHAINS                 5:0
#define NV_PGRAPH_PRI_FECS_ARB_CTX_ADR                    0x409a24
#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR                    0x409a0c
#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_PTR                    27:0
#define NV_PGRAPH_PRI_FECS_ARB_CTX_PTR_TARGET                29:28
#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD                    0x409a10
#define NV_PGRAPH_PRI_FECS_ARB_CTX_CMD_CMD                     4:0
#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP0                     0x40780c
#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP1                     0x407810
#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP2                     0x407814
#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP3                     0x407818
#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP4                     0x40781c
#define NV_PGRAPH_PRI_RSTR2D_GPC_MAP5                     0x407820
#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG             0x4078bc
#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_ROW_OFFSET       7:0
#define NV_PGRAPH_PRI_RSTR2D_MAP_TABLE_CONFIG_NUM_ENTRIES     15:8
#define NV_PGRAPH_PRI_PD_HWW_ESR                          0x406018
#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET                       30:30
#define NV_PGRAPH_PRI_PD_HWW_ESR_RESET_ACTIVE                    1
#define NV_PGRAPH_PRI_PD_HWW_ESR_EN                          31:31
#define NV_PGRAPH_PRI_PD_HWW_ESR_EN_ENABLE                       1
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC(i)     (0x406028+((i)*4))
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC__SIZE_1                 4
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT0                3:0
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT1                7:4
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT2               11:8
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT3              15:12
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT4              19:16
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT5              23:20
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT6              27:24
#define NV_PGRAPH_PRI_PD_NUM_TPC_PER_GPC_COUNT7              31:28
#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0                 0x4064c0
#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE   31:31
#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_EN    1
#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_0_TIMESLICE_ENABLE_DIS   0
#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1                 0x4064c4
#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES         15:0
#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_BATCHES_INIT  0xffff
#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT         26:16
#define NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1_MAX_OUTPUT_GRANULARITY          0x80
#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE(i)   (0x406800+((i)*4))
#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE__SIZE_1           0x100
#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N0_MASK        7:0
#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N1_MASK       15:8
#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N2_MASK      23:16
#define NV_PGRAPH_PRI_PD_ALPHA_RATIO_TABLE_GPC_4N3_MASK      31:24
#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE(i)    (0x406c00+((i)*4))
#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE__SIZE_1            0x100
#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N0_MASK         7:0
#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N1_MASK        15:8
#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N2_MASK       23:16
#define NV_PGRAPH_PRI_PD_BETA_RATIO_TABLE_GPC_4N3_MASK       31:24
#define NV_PGRAPH_PRI_DS_DEBUG                            0x405800
#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE                27:27
#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_DISABLE            0
#define NV_PGRAPH_PRI_DS_DEBUG_TIMESLICE_MODE_ENABLE             1
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R                      0x405804
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_R_VAL                      31:0
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G                      0x405808
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_G_VAL                      31:0
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B                      0x40580c
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_B_VAL                      31:0
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A                      0x405810
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_A_VAL                      31:0
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT                    0x405814
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL                     6:0
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_INVALID               0
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_ZERO                  1
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE             2
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32   4
#define NV_PGRAPH_PRI_DS_ZBC_COLOR_FMT_VAL_A8B8G8R8           0x28
#define NV_PGRAPH_PRI_DS_ZBC_Z                            0x405818
#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL                            31:0
#define NV_PGRAPH_PRI_DS_ZBC_Z_VAL__INIT                         0
#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT                        0x40581c
#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL                         0:0
#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_INVALID                   0
#define NV_PGRAPH_PRI_DS_ZBC_Z_FMT_VAL_FP32                      1
#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX                    0x405820
#define NV_PGRAPH_PRI_DS_ZBC_TBL_INDEX_VAL                     3:0
#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD                       0x405824
#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT                     0:0
#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_C                     0
#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_SELECT_Z                     1
#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION                     1:1
#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_ACTION_WRITE                 0
#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER                    2:2
#define NV_PGRAPH_PRI_DS_ZBC_TBL_LD_TRIGGER_ACTIVE               1
#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC              0x405830
#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE     27:16
#define NV_PGRAPH_PRI_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE     11:0
#define NV_PGRAPH_PRI_DS_HWW_ESR                          0x405840
#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET                       30:30
#define NV_PGRAPH_PRI_DS_HWW_ESR_RESET_TASK                      1
#define NV_PGRAPH_PRI_DS_HWW_ESR_EN                          31:31
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK                  0x405844
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR              0:0
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR              1:1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR              2:2
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR              3:3
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR              4:4
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR              5:5
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR              6:6
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR              7:7
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR              8:8
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR              9:9
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT         1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR           10:10
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR           11:11
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR           12:12
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR           13:13
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR           14:14
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR           15:15
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR           16:16
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR           17:17
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR           18:18
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR           19:19
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR           20:20
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR           21:21
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR           22:22
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR           23:23
#define NV_PGRAPH_PRI_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT        1
#define NV_PGRAPH_PRI_DS_MPIPE_STATUS                     0x405858
#define NV_PGRAPH_PRI_DS_NUM_TPC_PER_GPC(i)     (0x405870+((i)*4))
#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE               0x408004
#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8         31:0
#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS 8
#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE               0x408008
#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B          10:0
#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B__PROD      24
#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY    0x100
#define NV_PGRAPH_PRI_SCC_RM_BUNDLE_CB_SIZE_VALID            31:31
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE                0x40800c
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8          31:0
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS  8
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL                     0x408010
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES              7:0
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX          0
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE 0x80
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY       0x100
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_MAX_VALID_PAGES         15:8
#define NV_PGRAPH_PRI_SCC_RM_PAGEPOOL_VALID                  31:31
#define NV_PGRAPH_PRI_SCC_INIT                            0x40802c
#define NV_PGRAPH_PRI_SCC_INIT_RAM                             0:0
#define NV_PGRAPH_PRI_SCC_INIT_RAM_TRIGGER                       1
#define NV_PGRAPH_PRI_SCC_HWW_ESR                         0x408030
#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET                      30:30
#define NV_PGRAPH_PRI_SCC_HWW_ESR_RESET_ACTIVE                   1
#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN                         31:31
#define NV_PGRAPH_PRI_SCC_HWW_ESR_EN_ENABLE                      1
#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE          0x502420
#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0       0x502c04
#define NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1           0x502400
#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC                   0x502608
#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS     4:0
#define NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16
#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON               0x502620
#define NV_PGRAPH_PRI_GPC0_GPCCS_CFG_FALCON_IMEM_SZ            7:0
#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES                 0x502880
#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANES_NUM_CHAINS           5:0
#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE(i)            (0x502910+((i)*0))
#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE__SIZE_1           16
#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V               23:0
#define NV_PGRAPH_PRI_GPC0_GPCCS_RC_LANE_SIZE_V_0                0
#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0            0x502c80
#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1            0x502c84
#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2            0x502c88
#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3            0x502c8c
#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION            0x502c90
#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_TPC           23:16
#define NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN         0x502c94
#define NV_PGRAPH_PRI_GPC0_ZCULL_FS                       0x500910
#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_SMS                    8:0
#define NV_PGRAPH_PRI_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS         19:16
#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR                 0x500914
#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC  3:0
#define NV_PGRAPH_PRI_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET          11:8
#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP               0x500918
#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE      23:0
#define NV_PGRAPH_PRI_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX         0x800000
#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE           0x500920
#define NV_PGRAPH_PRI_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS  15:0
#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE(i)     (0x500a04+((i)*32))
#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_HEIGHT                12:1
#define NV_PGRAPH_PRI_GPC0_ZCULL_ZCSIZE_WIDTH                28:16
#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS             0x500c08
#define NV_PGRAPH_PRI_GPC0_GPM_PD_ACTIVE_TPCS_NUM              2:0
#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID(i)      (0x500c10+((i)*4))
#define NV_PGRAPH_PRI_GPC0_GPM_PD_SM_ID_ID                     7:0
#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS             0x500c8c
#define NV_PGRAPH_PRI_GPC0_GPM_SD_ACTIVE_TPCS_NUM              2:0
#define NV_PGRAPH_PRI_GPC0_GCC_DBG                        0x501000
#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0       0x504500
#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION       0x504508
#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM         1:1
#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN    0x50450c
#define NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM      1:1
#define NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x504238
#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID               0x504088
#define NV_PGRAPH_PRI_GPC0_TPC0_PE_CFG_SMID_VALUE             15:0
#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_DBG                   0x5044b0
#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID              0x5044e8
#define NV_PGRAPH_PRI_GPC0_TPC0_L1C_CFG_SMID_VALUE            15:0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0      0x504604
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1      0x504608
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0           0x50460c
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE            0:0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0          0x504610
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF           0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON            1
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP          1:1
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE    0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM            2:2
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE      0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK            1
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER            31:31
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE         1
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE        0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_WARP_VALID_MASK_0 0x504614
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_0  0x504624
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_0   0x504634
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR           0x504648
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR         15:0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE       0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_HWW_GLOBAL_ESR         0x504650
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0          0x50465c
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1          0x504660
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2          0x504664
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3          0x504668
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4          0x50466c
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS            0x504670
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0      0x504674
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1      0x504678
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2      0x50467c
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3      0x504680
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4      0x504684
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5      0x504688
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6      0x50468c
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7      0x504690
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG                 0x504698
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CONFIG_SM_ID               15:0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH                   0x50469c
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_WARP_COUNT             7:0
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_ARCH_SPA_VERSION           11:8
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_CACHE_CONTROL          0x5046a4
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL          0x504730
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL          0x504734
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL          0x504738
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL          0x50473c
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL          0x504740
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL          0x504744
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL          0x504748
#define NV_PGRAPH_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL          0x50474c
#define NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0       0x504d00
#define NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0       0x501d00
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL            0x41a100
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_CPUCTL_STARTCPU        1:1
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_HWCFG             0x41a108
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL            0x41a10c
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMACTL_REQUIRE_CTX     0:0
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC(i)           (0x41a180+((i)*16))
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_OFFS             7:2
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_BLK             15:8
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMC_AINCW          24:24
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMD(i)           (0x41a184+((i)*16))
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT(i)           (0x41a188+((i)*16))
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT__SIZE_1            4
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_IMEMT_TAG             15:0
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC(i)            (0x41a1c0+((i)*8))
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_OFFS             7:2
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_BLK             15:8
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMC_AINCW          24:24
#define NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_DMEMD(i)            (0x41a1c4+((i)*8))
#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX(i)           (0x41a800+((i)*4))
#define NV_PGRAPH_PRI_GPCS_GPCCS_CTXSW_MAILBOX_VALUE          31:0
#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0            0x41ac80
#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1            0x41ac84
#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2            0x41ac88
#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3            0x41ac8c
#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN         0x41ac94
#define NV_PGRAPH_PRI_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC        23:16
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE        0x418808
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8  31:0
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT            0
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE        0x41880c
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B   10:0
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 0
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_BUNDLE_CB_SIZE_VALID     31:31
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE        0x418810
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS    12
#define NV_PGRAPH_PRI_GPCS_SETUP_RM_ATTRIB_CB_BASE_VALID     31:31
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0                 0x418b08
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE0                2:0
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE1                7:5
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE2              12:10
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE3              17:15
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE4              22:20
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP0_TILE5              27:25
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1                 0x418b0c
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE6                2:0
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE7                7:5
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE8              12:10
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE9              17:15
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE10             22:20
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP1_TILE11             27:25
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2                 0x418b10
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE12               2:0
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE13               7:5
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE14             12:10
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE15             17:15
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE16             22:20
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP2_TILE17             27:25
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3                 0x418b14
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE18               2:0
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE19               7:5
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE20             12:10
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE21             17:15
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE22             22:20
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP3_TILE23             27:25
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4                 0x418b18
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE24               2:0
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE25               7:5
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE26             12:10
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE27             17:15
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE28             22:20
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP4_TILE29             27:25
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5                 0x418b1c
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE30               2:0
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE31               7:5
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE32             12:10
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE33             17:15
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE34             22:20
#define NV_PGRAPH_PRI_GPCS_CRSTR_GPC_MAP5_TILE35             27:25
#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG         0x418bb8
#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET   7:0
#define NV_PGRAPH_PRI_GPCS_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0    0x418980
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0  2:0
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1  6:4
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2 10:8
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3            14:12
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4            18:16
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5            22:20
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6            26:24
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7            30:28
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1    0x418984
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8  2:0
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9  6:4
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10            10:8
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11           14:12
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12           18:16
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13           22:20
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14           26:24
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15           30:28
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2    0x418988
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16 2:0
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17 6:4
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18            10:8
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19           14:12
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20           18:16
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21           22:20
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22           26:24
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23           30:28
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3    0x41898c
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24 2:0
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25 6:4
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26            10:8
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27           14:12
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28           18:16
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29           22:20
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30           26:24
#define NV_PGRAPH_PRI_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31           30:28
#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG                  0x418c6c
#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE        0:0
#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_DISABLE  0
#define NV_PGRAPH_PRI_GPCS_GPM_PD_CONFIG_TIMESLICE_MODE_ENABLE   1
#define NV_PGRAPH_PRI_GPCS_GCC_DBG                        0x419000
#define NV_PGRAPH_PRI_GPCS_GCC_DBG_INVALIDATE                  1:1
#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE           0x419004
#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_BASE_ADDR_39_8     31:0
#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL                0x419008
#define NV_PGRAPH_PRI_GPCS_GCC_RM_PAGEPOOL_TOTAL_PAGES         7:0
#define NV_PGRAPH_PRI_GPCS_MMU_CTRL                       0x418880
#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VM_PG_SIZE                 0:0
#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_VOL_FAULT                  1:1
#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_COMP_FAULT                 2:2
#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MISS_GRAN                  4:3
#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_CACHE_MODE                 6:5
#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_APERTURE             29:28
#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_VOL                  30:30
#define NV_PGRAPH_PRI_GPCS_MMU_CTRL_MMU_DISABLE              31:31
#define NV_PGRAPH_PRI_GPCS_MMU_PM_UNIT_MASK               0x418890
#define NV_PGRAPH_PRI_GPCS_MMU_PM_REQ_MASK                0x418894
#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL                 0x4188b0
#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL_DEBUG              16:16
#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_WR                   0x4188b4
#define NV_PGRAPH_PRI_GPCS_MMU_DEBUG_RD                   0x4188b8
#define NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0       0x41c500
#define NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0       0x41cd00
#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0       0x419d00
#define NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN    0x419d0c
#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF                    0x41980c
#define NV_PGRAPH_PRI_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH        4:4
#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR            0x419848
#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V  27:0
#define NV_PGRAPH_PRI_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID         28:28
#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG             0x419c00
#define NV_PGRAPH_PRI_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE   3:3
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0          0x419e10
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE 0:0
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON            1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER 30:30
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK            1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER            31:31
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE         1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE        0
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK           0x419e44
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR    1:1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR 2:2
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR 3:3
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP        4:4
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT   1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC  5:5
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW    6:6
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR 7:7
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG 8:8
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING 9:9
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO 10:10
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM 11:11
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR 12:12
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG      13:13
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT   1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR     14:14
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT  1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR 15:15
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE 16:16
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2 17:17
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC 18:18
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR 19:19
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT    20:20
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK         0x419e4c
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT 0:0
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR     1:1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS 2:2
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR 3:3
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT 1
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_HWW_GLOBAL_ESR         0x419e50
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL          0x419ea4
#define NV_PGRAPH_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_ICACHE         0:0
#define NV_PGRAPH_PRI_BE0_ZROP_STATUS                     0x410048
#define NV_PGRAPH_PRI_BE0_ZROP_STATUS2                    0x41004c
#define NV_PGRAPH_PRI_BE0_CROP_DEBUG3                     0x410108
#define NV_PGRAPH_PRI_BE0_CROP_STATUS1                    0x410134
#define NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0               0x410200
#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION               0x410204
#define NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN            0x410208
#define NV_PGRAPH_PRI_BES_ZROP_STATUS                     0x408848
#define NV_PGRAPH_PRI_BES_ZROP_STATUS2                    0x40884c
#define NV_PGRAPH_PRI_BES_CROP_DEBUG3                     0x408908
#define NV_PGRAPH_PRI_BES_CROP_STATUS1                    0x408934
#define NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0               0x408a00
#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC               32
#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC       32

#endif /* __nv_gf108_graphics_nobundle_hwref_h__ */