Bug 1477929 - Use a stricter constraint for the register passed to cbz. r=fkiefer

libfreebl3.so fails to build on arm with LTO enabled with the following
error:

     INFO -  <inline asm>:2:9: error: operand must be a register in range [r0, r7]
     INFO -  cbz     r10, 2f
     INFO -          ^
     INFO -  LLVM ERROR: Error parsing inline asm

It's not clear from the ARM documentation for CBZ whether that's a
problem with llvm or a limitation of the CBZ instruction, but at least
the version of LLVM we use insists that CBZ is used with a core register
(between r0 and r7, included).

That instruction comes from inline asm blocks, and in normal builds, it
just happens to work because the variable that is passed to CBZ is a
function argument, one of the four first arguments, such that it is
register allocated. The compiler just decides to use that register
directly.

With LTO, the function actually ends up inlined in its caller, and the
register allocated to the variable can end up outside the core register
range.

The GCC documentation for machine-constraints indicates the `l`
constraint exists to limit the possible registers:
 "In Thumb State the core registers r0-r7. In ARM state this is an alias
for the r constraint."

(CBZ being only used on thumb)

1 files changed, 2 insertions, 2 deletions

diff --git a/lib/freebl/mpi/mpi_arm.c b/lib/freebl/mpi/mpi_arm.c
index b5139f28d..521bb462a 100644
--- a/lib/freebl/mpi/mpi_arm.c
+++ b/lib/freebl/mpi/mpi_arm.c
@@ -39,7 +39,7 @@ s_mpv_mul_d(const mp_digit *a, mp_size a_len, mp_digit b, mp_digit *c)
         "2:\n"
         "str     r5, [%3]\n"
         :
-        : "r"(a), "r"(a_len), "r"(b), "r"(c)
+        : "r"(a), "l"(a_len), "r"(b), "r"(c)
         : "memory", "cc", "%r4", "%r5", "%r6");
 }
 
@@ -72,7 +72,7 @@ s_mpv_mul_d_add(const mp_digit *a, mp_size a_len, mp_digit b, mp_digit *c)
         "2:\n"
         "str     r5, [%3]\n"
         :
-        : "r"(a), "r"(a_len), "r"(b), "r"(c)
+        : "r"(a), "l"(a_len), "r"(b), "r"(c)
         : "memory", "cc", "%r4", "%r5", "%r6");
 }