From 9ecea72ce67de8f630142dcaeab51f01426d55ea Mon Sep 17 00:00:00 2001
From: Wan-Teh Chang <wtc@google.com>
Date: Sun, 27 Apr 2014 20:04:51 -0700
Subject: Bug 979703: Avoid _xgetbv() for 32-bit x86 builds so that we can use
 the Intel AES assembly code with VC 2010 RTM. r=cviecco.

---
 lib/freebl/Makefile   |  6 +++---
 lib/freebl/rijndael.c | 11 +++++++++++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/lib/freebl/Makefile b/lib/freebl/Makefile
index dbf386200..2a51501bb 100644
--- a/lib/freebl/Makefile
+++ b/lib/freebl/Makefile
@@ -135,9 +135,9 @@ else
     ifdef BUILD_OPT
 	OPTIMIZER += -Ox  # maximum optimization for freebl
     endif
-    # The Intel AES assembly code requires Visual C++ 2010 (10.0). The _xgetbv
-    # compiler intrinsic function requires Visual C++ 2010 (10.0) SP1.
-    ifeq ($(_MSC_VER_GE_10SP1),1)
+    # The Intel AES assembly code requires Visual C++ 2010.
+    # if $(_MSC_VER) >= 1600 (Visual C++ 2010)
+    ifeq ($(firstword $(sort $(_MSC_VER) 1600)),1600)
 	DEFINES += -DUSE_HW_AES -DINTEL_GCM
 	ASFILES += intel-aes-x86-masm.asm intel-gcm-x86-masm.asm
 	EXTRA_SRCS += intel-gcm-wrap.c
diff --git a/lib/freebl/rijndael.c b/lib/freebl/rijndael.c
index 67057c701..4e4be79fd 100644
--- a/lib/freebl/rijndael.c
+++ b/lib/freebl/rijndael.c
@@ -972,13 +972,24 @@ AESContext * AES_AllocateContext(void)
 /*
  * Adapted from the example code in "How to detect New Instruction support in
  * the 4th generation Intel Core processor family" by Max Locktyukhin.
+ *
+ * XGETBV:
+ *   Reads an extended control register (XCR) specified by ECX into EDX:EAX.
  */
 static PRBool
 check_xcr0_ymm()
 {
     PRUint32 xcr0;
 #if defined(_MSC_VER)
+#if defined(_M_IX86)
+    __asm {
+        mov ecx, 0
+        xgetbv
+        mov xcr0, eax
+    }
+#else
     xcr0 = (PRUint32)_xgetbv(0);  /* Requires VS2010 SP1 or later. */
+#endif
 #else
     __asm__ ("xgetbv" : "=a" (xcr0) : "c" (0) : "%edx");
 #endif
-- 
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