From a5cf364d1116025f1ec8cf253e8092c4ba83c5af Mon Sep 17 00:00:00 2001 From: Makoto Kato Date: Fri, 25 Jun 2021 08:18:13 +0000 Subject: Bug 1655493 - Support SHA2 HW acceleration using Intel SHA Extension. r=bbeurdouche Before applying (on Ryzen 9 3900X) ``` # mode in opreps cxreps context op time(sec) thrgput sha256_e 1Gb 208Mb 23M 0 0.000 10000.000 10.000 123Mb 301Kb ``` After applying ``` # mode in opreps cxreps context op time(sec) thrgput sha256_e 5Gb 797Mb 110M 0 0.000 10000.000 10.000 591Mb 769Kb ``` Differential Revision: https://phabricator.services.mozilla.com/D116962 --- coreconf/WIN32.mk | 2 ++ coreconf/config.gypi | 1 + 2 files changed, 3 insertions(+) (limited to 'coreconf') diff --git a/coreconf/WIN32.mk b/coreconf/WIN32.mk index 9e04ad93e..f5db943cf 100644 --- a/coreconf/WIN32.mk +++ b/coreconf/WIN32.mk @@ -56,6 +56,8 @@ else _MSC_VER_GE_11 := $(shell expr $(_MSC_VER) \>= 1700) # VC12 (2013). _MSC_VER_GE_12 := $(shell expr $(_MSC_VER) \>= 1800) + # VC14 (2015). + _MSC_VER_GE_14 := $(shell expr $(_MSC_VER) \>= 1900) ifeq ($(_CC_VMAJOR),14) # -DYNAMICBASE is only supported on VC8SP1 or newer, # so be very specific here! diff --git a/coreconf/config.gypi b/coreconf/config.gypi index 5800f8791..0867ba2c9 100644 --- a/coreconf/config.gypi +++ b/coreconf/config.gypi @@ -99,6 +99,7 @@ 'disable_arm_hw_aes%': 0, 'disable_arm_hw_sha1%': 0, 'disable_arm_hw_sha2%': 0, + 'disable_intel_hw_sha%': 0, 'disable_tests%': 0, 'disable_chachapoly%': 0, 'disable_deprecated_seed%': 0, -- cgit v1.2.1