From ca5bbef466b5c7ba899fbf69078049d6abbcce96 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 11 Feb 2015 12:25:38 -0700 Subject: Support Tegra210 Tegra210 changes the pinmux HW in a few ways; at least: - The set of drive groups is much more 1:1 with the set of pins. Most pins have an associated drive group register as well as an associated pinmux register, and most drive groups cover a single pin. - Some register fields have moved from the drive group registers into the pinmux registers. - The set of available options for each pin and group varies relative to previous chips, and hence the register layouts vary a bit too. This patch updates tegra-pinmux-scripts minimally to handle these changes, to a level equivalent to the support for previous chips. For example, some new options such as per-pin schmitt aren't handled since the syseng-supplied pinmux spreadsheets don't provide a value for this option. csv-to-board-tegra124-xlsx.py is renamed to csv-to-board.py since it now supports boards using different SoCs, and it's not worth encoding all supported SoCs in the filename (Tegra30/114 aren't supported by it, hence the previous naming). Signed-off-by: Stephen Warren --- tegra_pmx_board_parser.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'tegra_pmx_board_parser.py') diff --git a/tegra_pmx_board_parser.py b/tegra_pmx_board_parser.py index 1ea16ef..b72bc8b 100644 --- a/tegra_pmx_board_parser.py +++ b/tegra_pmx_board_parser.py @@ -29,8 +29,10 @@ configs_dir = os.path.join(script_dir, 'configs') class PinConfig(ReprDictObj): def __init__(self, soc, data): fields = ('fullname', 'mux', 'gpio_init', 'pull', 'tri', 'e_inp', 'od') - if soc.has_rcv_sel: + if soc.soc_pins_have_rcv_sel: fields += ('rcv_sel', ) + if soc.soc_pins_have_e_io_hv: + fields += ('e_io_hv', ) for i, field in enumerate(fields): self.__setattr__(field, data[i]) self.gpio_pin = soc.gpio_or_pin_by_fullname(self.fullname) -- cgit v1.2.1