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author | Jacques Garrigue <garrigue at math.nagoya-u.ac.jp> | 2004-01-28 13:58:36 +0000 |
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committer | Jacques Garrigue <garrigue at math.nagoya-u.ac.jp> | 2004-01-28 13:58:36 +0000 |
commit | 15a6cf84827a43fc83c8c8fa1ef838c2c92964f0 (patch) | |
tree | d919700af9e2030b130038c67abf086345fa9475 | |
parent | 450d2a54022bb7d948336d7db50bf0cfdd34fcdf (diff) | |
download | ocaml-15a6cf84827a43fc83c8c8fa1ef838c2c92964f0.tar.gz |
emit more lea
git-svn-id: http://caml.inria.fr/svn/ocaml/branches/newoolab@6090 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
-rw-r--r-- | asmcomp/i386/emit.mlp | 16 | ||||
-rw-r--r-- | asmcomp/i386/emit_nt.mlp | 16 | ||||
-rw-r--r-- | asmcomp/i386/selection.ml | 4 |
3 files changed, 33 insertions, 3 deletions
diff --git a/asmcomp/i386/emit.mlp b/asmcomp/i386/emit.mlp index 337e79cafc..17c0362f3e 100644 --- a/asmcomp/i386/emit.mlp +++ b/asmcomp/i386/emit.mlp @@ -609,7 +609,21 @@ let emit_instr fallthrough i = ` addl $8, %esp\n`; stack_offset := !stack_offset + 8 | Lop(Ispecific(Ilea addr)) -> - ` lea {emit_addressing addr i.arg 0}, {emit_reg i.res.(0)}\n` + begin match addr with + Iindexed n when i.arg.(0).loc = i.res.(0).loc -> + if n = 1 then + ` incl {emit_reg i.res.(0)}\n` + else if n = -1 then + ` decl {emit_reg i.res.(0)}\n` + else + ` addl ${emit_int n}, {emit_reg i.res.(0)}\n` + | Iindexed2 0 when i.arg.(0).loc = i.res.(0).loc -> + ` addl {emit_reg i.arg.(1)}, {emit_reg i.res.(0)}\n` + | Iindexed2 0 when i.arg.(1).loc = i.res.(0).loc -> + ` addl {emit_reg i.arg.(0)}, {emit_reg i.res.(0)}\n` + | _ -> + ` lea {emit_addressing addr i.arg 0}, {emit_reg i.res.(0)}\n` + end | Lop(Ispecific(Istore_int(n, addr))) -> ` movl ${emit_nativeint n}, {emit_addressing addr i.arg 0}\n` | Lop(Ispecific(Istore_symbol(s, addr))) -> diff --git a/asmcomp/i386/emit_nt.mlp b/asmcomp/i386/emit_nt.mlp index 19e8032b85..8a733b52be 100644 --- a/asmcomp/i386/emit_nt.mlp +++ b/asmcomp/i386/emit_nt.mlp @@ -586,7 +586,21 @@ let emit_instr i = ` add esp, 8\n`; stack_offset := !stack_offset + 8 | Lop(Ispecific(Ilea addr)) -> - ` lea {emit_reg i.res.(0)}, DWORD PTR {emit_addressing addr i.arg 0}\n` + begin match addr with + Iindexed n when i.arg.(0).loc = i.res.(0).loc -> + if n = 1 then + ` inc {emit_reg i.res.(0)}\n` + else if n = -1 then + ` dec {emit_reg i.res.(0)}\n` + else + ` add {emit_reg i.res.(0)}, {emit_int n}\n` + | Iindexed2 0 when i.arg.(0).loc = i.res.(0).loc -> + ` add {emit_reg i.res.(0)}, {emit_reg i.arg.(1)}\n` + | Iindexed2 0 when i.arg.(1).loc = i.res.(0).loc -> + ` add {emit_reg i.res.(0)}, {emit_reg i.arg.(0)}\n` + | _ -> + ` lea {emit_reg i.res.(0)}, DWORD PTR {emit_addressing addr i.arg 0}\n` + end | Lop(Ispecific(Istore_int(n, addr))) -> ` mov DWORD PTR {emit_addressing addr i.arg 0},{emit_nativeint n}\n` | Lop(Ispecific(Istore_symbol(s, addr))) -> diff --git a/asmcomp/i386/selection.ml b/asmcomp/i386/selection.ml index f2f79ca5e7..621cb8de38 100644 --- a/asmcomp/i386/selection.ml +++ b/asmcomp/i386/selection.ml @@ -192,7 +192,9 @@ method select_operation op args = (* Recognize the LEA instruction *) Caddi | Cadda | Csubi | Csuba -> begin match self#select_addressing (Cop(op, args)) with - (Iindexed d, _) -> super#select_operation op args + (addr, (Cvar _ | Ctuple[Cvar _; Cvar _] as arg)) -> + (Ispecific(Ilea addr), [arg]) + | (Iindexed _, _) | (Iindexed2 0, _) -> super#select_operation op args | (addr, arg) -> (Ispecific(Ilea addr), [arg]) end |