From 0c0c5f940a3fc58c84b51765fc04f0294b42fd2d Mon Sep 17 00:00:00 2001
From: Jean-Marc Valin <jean-marc.valin@usherbrooke.ca>
Date: Mon, 7 Mar 2011 20:54:33 -0500
Subject: Support for glitchles mode switching

Uses a 5ms redundant CELT frame embedded into the SILK or hybrid
packet to handle the switching. It's still possible to use the
PLC-based method when no redundant packet is included.
---
 silk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'silk/PLC.h')

diff --git a/silk b/silk
index 37f9809a..20832a6c 160000
--- a/silk
+++ b/silk
@@ -1 +1 @@
-Subproject commit 37f9809a68b6c5ba514b0642e99231a7f68ee86d
+Subproject commit 20832a6c95a84e18da936228e4b15823d8b89728
-- 
cgit v1.2.1