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* Fix endianity detection on SolarisMartin Mares2014-11-011-1/+9
| | | | Patch by Philip Brown.
* lspci: Correct Root Capabilities "CRS Software Visibility" bitBjorn Helgaas2014-11-011-1/+1
| | | | | | | | | | lspci incorrectly tests bit 4, not bit 0, for "CRS Software Visibility" in the Root Capabilities register, so it shows "RootCap: CRSVisible-" even for devices that do support Software Visibility. Use the correct definition for PCI_EXP_RTCAP_CRSVIS. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Decode Interrupt Pin and Interrupt Line for PCI-PCI bridgesBjorn Helgaas2014-11-011-1/+1
| | | | | | | Bridges can implement interrupt pins, so decode this information. See PCI-to-PCI Bridge spec r1.2, sec 3.2.5.17. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* Clean up reading of device labelsMartin Mares2014-11-011-2/+1
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* lspci: Show device name as exported by BIOS (sysfs label attribute) (V2)Thomas Renninger2014-11-014-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Device name of a PCI or PCI Express device under OS may be exported via ACPI _DSM function with function index 7. This allows to connect a described PCI device in the platform documentation or as labeled on the chassis with PCI devices shown via lspci. The kernel already exports this string through sysfs under a PCI device through the "label" sysfs attribute. This patch reads the device name if available and shows it to the user. Real world examples: Device Name: "USB HS EHCI Controller #2 #3" Device Name: "USB HS EHCI Controller #1" Device Name: "SATA Controller #1" Device Name: "Onboard LAN #1" Device Name: "Onboard LAN #2" Device Name: "Onboard Video (PILOT-3)" Compare with PCI Firmware Spec v3.1 chapter 4.6.7 and ACPI spec v5.0 chapter 9.14.1 The DeviceName is not shown by default, but starting from first verbose parameter (-v). V2: - Free label string if allocated - Enhance changelog Signed-off-by: Thomas Renninger <trenn@suse.de> CC: linux-pci@vger.kernel.org
* Avoid C99 constructionsFrançois Revol2014-11-011-1/+1
| | | | | | This fixes building pciutils on Haiku. Signed-off-by: François Revol <revol@free.fr>
* <asm/io.h> does not exist any moreMartin Mares2014-11-011-4/+0
| | | | Thanks to John Spencer for bringing this to attention.
* Do not forget to include <stdio.h>Martin Mares2014-11-011-0/+1
| | | | Suggested by John Spencer.
* lspci: Decode ASPMOptComp bit in LnkCap registerMartin Mares2014-02-252-2/+4
| | | | Patch by Robert Elliott from HP.
* Fixed a typo in messages printed in map modeMartin Mares2013-12-101-1/+1
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* maint/tag-release: Use my kernel.org key to sign releasesv3.2.1Martin Mares2013-11-101-1/+1
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* Released as 3.2.1.Martin Mares2013-11-102-2/+18
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* Updated pci.ids to today's snapshotMartin Mares2013-11-101-534/+2239
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* sysfs: Do not warn on incomplete slot addressesMartin Mares2013-11-101-2/+11
| | | | Based on a patch by Zheng Huai Cheng <zhenghch@linux.vnet.ibm.com>.
* lspci: Drop PCIe LnkCtl "Retrain Link" decodingBjorn Helgaas2013-11-101-2/+1
| | | | | | | Per PCIe spec r3.0, Table 7-16, the Retrain Link bit is writable but always returns 0 when read, so decoding it gives no useful information. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Decode PCIe LnkCtl "Read Completion Boundary" for PCIe-to-PCI bridgesBjorn Helgaas2013-11-101-1/+1
| | | | | | | | | | The PCIe spec (r3.0, Table 7-16) says the Read Completion Boundary is valid for Root Ports, Endpoints, and Bridges. I only added decoding for PCIe-to- PCI/PCI-X bridges because the RCB of a Bridge indicates the RCB of the upstream Root Port, so I don't think it makes sense for PCI-to-PCIe bridges. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Clarify "PCIe-to-PCI/PCI-X" desc and Bridge Retry Config EnableBjorn Helgaas2013-11-102-4/+4
| | | | | | | | | | The PCI_EXP_TYPE_PCI_BRIDGE type is a PCIe to PCI/PCI-X bridge, so be a bit more complete in the comment and printed device type. Also, per PCIe spec r3.0, Table 7-14, the PCIe Device Control "Bridge Configuration Retry Enable" bit only applies to PCIe-to-PCI/PCI-X bridges; it does not apply to PCI-to-PCIe bridges. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Decode PCIe DevCap/DevCtl FLReset only for EndpointsBjorn Helgaas2013-11-101-4/+7
| | | | | | | | The PCIe Device Capabilities and Control bits related to Function Level Reset are valid only for Endpoints, so only decode them in that case. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Decode PCIe DevCap "Acceptable Latencies" only for EndpointsBjorn Helgaas2013-11-101-2/+5
| | | | | | | | The PCIe Device Capabilities "Endpoint L0s Acceptable Latency" and "Endpoint L1 Acceptable Latency" are defined only for Endpoint functions, so don't display them unless this is an endpoint. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Label PCIe LnkCap "L0s Exit Latency" as "L0s", not "L0"Bjorn Helgaas2013-11-101-1/+1
| | | | | | | | | | | The PCIe Link Capabilities "L0s Exit Latency" is the latency to exit L0s, not L0, so label it "L0s" instead of "L0". This matches the way we label the Device Capabilities "Endpoint L0s Acceptable Latency" field as "Latency L0s". This also adds "Exit" to the description to help distinguish it from the "Acceptable Latency" fields in the Device Capabilities register. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Decode PCIe Link registers only for devices with linksBjorn Helgaas2013-11-101-2/+7
| | | | | | | | Root Complex Integrated Endpoints and Root Complex Event Collectors do not have links and are not permitted to implement Link or Link 2 registers, per PCIe spec r3.0, sec 1.3.2.3. Decoding them is useless and misleading. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Make output of L1 PM cap consistent with other capsMartin Mares2013-06-111-2/+2
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* Added a test case for the L1 PM capabilityMartin Mares2013-06-111-0/+26
| | | | Based on data contributed by David Box.
* lspci: Add L1 PM Substate capability reportingDavid Box2013-06-112-0/+56
| | | | | | | Expose available L1 substate capabilities that can enable lower power consumption when a PCIe Link is idle. Signed-off-by: David Box <david.e.box@linux.intel.com>
* lspci: Fully decode ASPM support from Link CapabilitiesBjorn Helgaas2013-05-201-0/+2
| | | | | | | | | The ASPM Support field in Link Capabilities is two bits, and all four possible encodings are defined as of PCIe spec r3.0. Previously, lspci only decoded values 1, 2, and 3. This adds 0, so lspci will show "ASPM not supported" instead of "ASPM unknown". Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* lspci: Display CardBus bridge capabilitiesMatthew Wilcox2013-04-204-6/+8
| | | | | | | | CardBus bridges can have capabilities, but the CAP_PTR register is at a different location. This one has Power Management: CardBus bridge: O2 Micro, Inc. OZ711SP1 Memory CardBus Controller (rev 01) + Capabilities: [a0] Power Management version 2
* maint/KORG-NOTES: Private maintainer's notes about kernel.orgMartin Mares2013-04-191-0/+4
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* maint/release: metalab.unc.edu does not accept submissions any longerMartin Mares2013-04-191-4/+0
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* Released as 3.2.0.v3.2.0Martin Mares2013-04-192-3/+15
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* Updated pci.ids to today's snapshotMartin Mares2013-04-191-1252/+2915
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* lspci: Better filtering of duplicate kernel module namesMartin Mares2013-04-191-8/+24
| | | | | | It was implemented only for reading modules.pcimap, but it turned out that it is necessary for libkmod, too, so we have switched to a common implementation.
* Minor cleanup of the previous patchMartin Mares2013-04-011-7/+8
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* install: split out pcilib install to a dedicated targetKevin Pyle2013-04-011-5/+9
| | | | | | | The "install" target manages one set of files, and the "install-pcilib" target manages a different set. They both install the pci library though so if you try to run `make -j install install-pcilib`, things randomly fail. So split out the commonly installed files into a dedicated target.
* lib/configure: match all freebsd os'sMarek Cruz2013-04-011-1/+1
| | | | | | When using targets like "i686-pc-freebsd7.1", the configure script fails to match for the freebsd target because it only expects "freebsd". Add a glob to match all freebsd targets.
* Squash an unused variable warningMartin Mares2013-04-011-1/+2
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* setpci: ~0UL should be ~0U, no longs are involved anymoreMartin Mares2013-04-011-2/+2
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* Configure: pkg-config can be overridden by $PKG_CONFIGMartin Mares2013-04-011-5/+8
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* On newer Linux systems, use libkmod to look up kernel modulesMartin Mares2013-04-015-26/+184
| | | | | With modutils built upon libkmod, modules.pcimap does not exist any longer.
* Use symbol versioning for our new member of struct pci_devMartin Mares2013-04-017-8/+18
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* Detection of module aliases (Linux sysfs only)Martin Mares2013-04-013-10/+33
| | | | This will be needed to support libkmod.
* Fixed logic error in pci_open()Martin Mares2012-12-061-1/+1
| | | | | Previously, pci_open() sometimes crashed with ID list names shorter than 3 characters.
* Released as 3.1.10.v3.1.10Martin Mares2012-06-252-2/+12
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* Updated pci.ids to today's snapshotMartin Mares2012-06-251-330/+852
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* Display whether LTR/OBFF are supported and enabledMika Westerberg2012-06-122-4/+44
| | | | | | | DEVCAP2 and DEVCTL2 capabilities contain information whether LTR and OBFF are supported and enabled. Make sure this is displayed to user as well. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
* Only decode defined fields of PCI Express Link Control 2Ben Hutchings2012-05-281-7/+13
| | | | | | | | | | | On a PCI Express multi-function device associated with an upstream port, all bits of the Link Control 2 register are currently reserved on functions > 0. The Selectable De-emphasis field is reserved on all but downstream ports. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
* pciutils: correct VC status displayJ.L. Burr2012-05-281-1/+1
| | | | | | | I think there is a bug displaying the virtual channel status bits "NegoPending" and "InProgress". The wrong offset is being used. Signed-off-by: John L. Burr <jlburr@cadence.com>
* Fix syntax error when PCI_COMPRESSED_IDS is empty.Ville Skyttä2012-05-281-1/+1
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* lspci: zero address in IO isn't always unassignedAaron Sierra2012-05-282-2/+2
| | | | | | | | | | | | | | | Zero is a valid address in I/O space, so display it and it's associated size when IO is enabled in the PCI command register. From arch/powerpc/kernel/pci-common.c: /* Here, we are a bit different than memory as typically IO space * starting at low addresses -is- valid. What we do instead [is] that * we consider as unassigned anything that doesn't have IO enabled * in the PCI command register, and that's it. */ Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
* Release scripts: Revived kernel.org Git repoMartin Mares2012-01-141-3/+3
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* Released as 3.1.9.v3.1.9Martin Mares2012-01-142-3/+19
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