Fix cache-flush issue on PowerPC, adding some comments and a check for disabled PCRE_EXTRA_TABLES.

git-svn-id: svn://vcs.exim.org/pcre/code/trunk@742 2f5784b3-3f2a-0410-8824-cb99058d5e15

5 files changed, 37 insertions, 5 deletions

diff --git a/ChangeLog b/ChangeLog
index bca62fe..b35b2d4 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -9,6 +9,10 @@ Version 8.21
 2.  JIT compiler now supports OP_NCREF, OP_RREF and OP_NRREF. New test cases
     are added as well.
 
+3.  Fix cache-flush issue on PowerPC (It is still an experimental JIT port).
+    PCRE_EXTRA_TABLES is not suported by JIT, and should be checked before
+    calling _pcre_jit_exec. Some extra comments are added.
+
 
 Version 8.20 21-Oct-2011
 ------------------------
diff --git a/pcre_exec.c b/pcre_exec.c
index d390ff4..2e763d1 100644
--- a/pcre_exec.c
+++ b/pcre_exec.c
@@ -6011,6 +6011,7 @@ matching. */
 if (extra_data != NULL
     && (extra_data->flags & PCRE_EXTRA_EXECUTABLE_JIT) != 0
     && extra_data->executable_jit != NULL
+    && (extra_data->flags & PCRE_EXTRA_TABLES) == 0
     && (options & ~(PCRE_NO_UTF8_CHECK | PCRE_NOTBOL | PCRE_NOTEOL |
                     PCRE_NOTEMPTY | PCRE_NOTEMPTY_ATSTART)) == 0)
   return _pcre_jit_exec(re, extra_data->executable_jit, subject, length,
diff --git a/sljit/sljitConfigInternal.h b/sljit/sljitConfigInternal.h
index 8ba1bb8..207dc18 100644
--- a/sljit/sljitConfigInternal.h
+++ b/sljit/sljitConfigInternal.h
@@ -178,13 +178,23 @@
 
 #ifndef SLJIT_CACHE_FLUSH
 
-#if !(defined SLJIT_CONFIG_X86_32 && SLJIT_CONFIG_X86_32) && !(defined SLJIT_CONFIG_X86_64 && SLJIT_CONFIG_X86_64)
-	/* Just call __ARM_NR_cacheflush on Linux. */
+#if (defined SLJIT_CONFIG_PPC_32 && SLJIT_CONFIG_PPC_32) || (defined SLJIT_CONFIG_PPC_64 && SLJIT_CONFIG_PPC_64)
+
+/* The __clear_cache() implementation of GCC is a dummy function on PowerPC. */
 #define SLJIT_CACHE_FLUSH(from, to) \
-	__clear_cache((char*)(from), (char*)(to))
-#else
-	/* Not required to implement on archs with unified caches. */
+	ppc_cache_flush((from), (to))
+
+#elif (defined SLJIT_CONFIG_X86_32 && SLJIT_CONFIG_X86_32) || (defined SLJIT_CONFIG_X86_64 && SLJIT_CONFIG_X86_64)
+
+/* Not required to implement on archs with unified caches. */
 #define SLJIT_CACHE_FLUSH(from, to)
+
+#else
+
+/* Calls __ARM_NR_cacheflush on ARM-Linux. */
+#define SLJIT_CACHE_FLUSH(from, to) \
+	__clear_cache((char*)(from), (char*)(to))
+
 #endif
 
 #endif /* !SLJIT_CACHE_FLUSH */
diff --git a/sljit/sljitLir.h b/sljit/sljitLir.h
index f519a4e..2a82968 100644
--- a/sljit/sljitLir.h
+++ b/sljit/sljitLir.h
@@ -56,6 +56,9 @@
         - mainly position independent code
       - Optimizations (perhaps later)
         - Only for basic blocks (when no labels inserted between LIR instructions)
+
+    For valgrind users:
+      - pass --smc-check=all argument to valgrind, since JIT is a "self-modifying code"
 */
 
 #if !(defined SLJIT_NO_DEFAULT_CONFIG && SLJIT_NO_DEFAULT_CONFIG)
@@ -87,6 +90,7 @@
 
 #define SLJIT_UNUSED		0
 
+/* Temporary (scratch) registers may not preserve their values across function calls. */
 #define SLJIT_TEMPORARY_REG1	1
 #define SLJIT_TEMPORARY_REG2	2
 #define SLJIT_TEMPORARY_REG3	3
@@ -95,6 +99,7 @@
 #define SLJIT_TEMPORARY_EREG1	4
 #define SLJIT_TEMPORARY_EREG2	5
 
+/* General (saved) registers preserve their values across function calls. */
 #define SLJIT_GENERAL_REG1	6
 #define SLJIT_GENERAL_REG2	7
 #define SLJIT_GENERAL_REG3	8
diff --git a/sljit/sljitNativePPC_common.c b/sljit/sljitNativePPC_common.c
index fcabcfc..af14b75 100644
--- a/sljit/sljitNativePPC_common.c
+++ b/sljit/sljitNativePPC_common.c
@@ -37,6 +37,18 @@ SLJIT_API_FUNC_ATTRIBUTE SLJIT_CONST char* sljit_get_platform_name()
    Both for ppc-32 and ppc-64. */
 typedef sljit_ui sljit_ins;
 
+static void ppc_cache_flush(sljit_ins *from, sljit_ins *to)
+{
+	while (from < to) {
+#ifdef __GNUC__
+		asm volatile ( "icbi 0, %0" : : "r"(from) );
+#else
+#error "Must implement icbi"
+#endif
+		from++;
+	}
+}
+
 #define TMP_REG1	(SLJIT_NO_REGISTERS + 1)
 #define TMP_REG2	(SLJIT_NO_REGISTERS + 2)
 #define TMP_REG3	(SLJIT_NO_REGISTERS + 3)