Move verilog package/import up in match order

Lines that have leading whitespace should now match correctly.
---
 pygments/lexers/hdl.py |    8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

1 files changed, 3 insertions, 5 deletions

diff --git a/pygments/lexers/hdl.py b/pygments/lexers/hdl.py
index f1e9f26d..0db35e74 100644
--- a/pygments/lexers/hdl.py
+++ b/pygments/lexers/hdl.py
@@ -147,6 +147,9 @@ class SystemVerilogLexer(RegexLexer):
     tokens = {
         'root': [
             (r'^\s*`define', Comment.Preproc, 'macro'),
+            (r'^(\s*)(package)(\s+)', bygroups(Text, Keyword.Namespace, Text)),
+            (r'^(\s*)(import)(\s+)', bygroups(Text, Keyword.Namespace, Text), 'import'),
+
             (r'\n', Text),
             (r'\s+', Text),
             (r'\\\n', Text), # line continuation
@@ -168,11 +171,6 @@ class SystemVerilogLexer(RegexLexer):
             (r'[()\[\],.;\']', Punctuation),
             (r'`[a-zA-Z_][a-zA-Z0-9_]*', Name.Constant),
 
-            (r'^\s*(package)(\s+)', bygroups(Keyword.Namespace, Text)),
-            (r'^\s*(import)(\s+)', bygroups(Keyword.Namespace, Text), 'import'),
-
-
-
             (r'(accept_on|alias|always|always_comb|always_ff|always_latch|'
              r'and|assert|assign|assume|automatic|before|begin|bind|bins|'
              r'binsof|bit|break|buf|bufif0|bufif1|byte|case|casex|casez|'