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authorGeorg Brandl <georg@python.org>2014-01-19 19:05:19 +0100
committerGeorg Brandl <georg@python.org>2014-01-19 19:05:19 +0100
commit3b5d25c8d1b9ff34ac24230f606355c49bf429ab (patch)
treed5c583dfac120c590f27048ed4d47daa12dc72a5 /pygments/lexers/hdl.py
parentff3a8dea781fb0492de4abbd4da48a5b1c110974 (diff)
downloadpygments-3b5d25c8d1b9ff34ac24230f606355c49bf429ab.tar.gz
use versionadded directives
Diffstat (limited to 'pygments/lexers/hdl.py')
-rw-r--r--pygments/lexers/hdl.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/pygments/lexers/hdl.py b/pygments/lexers/hdl.py
index 0ea9a7c5..1ebe4e5c 100644
--- a/pygments/lexers/hdl.py
+++ b/pygments/lexers/hdl.py
@@ -22,7 +22,7 @@ class VerilogLexer(RegexLexer):
"""
For verilog source code with preprocessor directives.
- *New in Pygments 1.4.*
+ .. versionadded:: 1.4
"""
name = 'verilog'
aliases = ['verilog', 'v']
@@ -134,7 +134,7 @@ class SystemVerilogLexer(RegexLexer):
Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
1800-2009 standard.
- *New in Pygments 1.5.*
+ .. versionadded:: 1.5
"""
name = 'systemverilog'
aliases = ['systemverilog', 'sv']
@@ -274,7 +274,7 @@ class VhdlLexer(RegexLexer):
"""
For VHDL source code.
- *New in Pygments 1.5.*
+ .. versionadded:: 1.5
"""
name = 'vhdl'
aliases = ['vhdl']